Document
NCP5210
3−in−1 PWM Dual Buck and Linear DDR Power Controller
The NCP5210, 3−in−1 PWM Dual Buck and Linear DDR Power Controller, is a complete power solution for MCH and DDR memory. This IC combines the efficiency of PWM controllers for the VDDQ supply and the MCH core supply voltage with the simplicity of linear regulator for the VTT termination voltage.
This IC contains two synchronous PWM buck controller for driving four external N−Ch FETs to form the DDR memory supply voltage (VDDQ) and the MCH regulator. The DDR memory termination regulator (VTT) is designed to track at the half of the reference voltage with sourcing and sinking current.
Protective features include, soft−start circuitry, undervoltage monitoring of 5VDUAL and BOOT voltage, and thermal shutdown. The device is housed in a thermal enhanced space−saving QFN−20 package.
Features
• Incorporates Synchronous PWM Buck Controllers for VDDQ and
VMCH
• Integrated Power FETs with VTT Regulator Source/Sink up to 2.0 A • All External Power MOSFETs are N−Channel • Adjustable VDDQ and VMCH by External Dividers • VTT Tracks at Half the Reference Voltage • Fixed Switching Frequency of 250 kHz for VDDQ and VMCH • Doubled Switching Frequency of 500 kHz for VDDQ Controller in
Standby Mode to Optimize Inductor Current Ripple and Efficiency
• Soft−Start Protection for all Controllers • Undervoltage Monitor of Supply Voltages • Overcurrent Protections for DDQ and VTT Regulators • Fully Complies with ACPI Power Sequencing Specifications • Short Circuit Protection Prevents Damage to Power Supply Due
to Reverse DIMM Insertion
• Thermal Shutdown • 5x6 QFN−20 Package • Pb−Free Package is Available*
Applications
• DDR I and DDR II Memory and MCH Power Supply
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING DIAGRAM
20
1
NCP5210
1
QFN−20
AWLYYWW
MN SUFFIX
CASE 505AB
NCP5210 = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
PIN CONNECTIONS
COMP FBDDQ
SS PGND
VTT VDDQ AGND FBVTT DDQ_REF FB1P5
SW_DDQ BG_DDQ TG_DDQ BOOT 5VDUAL COMP_1P5 BUF_Cut TG_1P5 BG_1P5 GND_1P5
NOTE: Pin 21 is the thermal pad on the bottom of the device.
ORDERING INFORMATION
Device
Package
Shipping†
NCP5210MNR2 QFN−20 2500 Tape & Reel
NCP5210MNR2G QFN−20 2500 Tape & Reel (Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2005
1
January, 2005 − Rev. 4
Publication Order Number: NCP5210/D
BUF_Cut
BUF_Cut SS
CSS
1.25 V, 2 Apk
VTT COUT2
VTT FBVTT
CZM2 R5
RZM2
R6 VMCH
VDDQ
AGND DDQ_REF
CZM1 RZM1
CPM1 COMP_1P5
5VDUAL
FB_1P5
M3 L
TG_1P5
1.5 V, 10 A
COUT3
M4
BG_1P5 GND_1P5
NCP5210
NCP5210
BOOT 5VDUAL
12 V
13 V Zener
5VDUAL
M1
TG_DDQ
L
S.