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74AUP1G240 Dataheets PDF



Part Number 74AUP1G240
Manufacturers NXP
Logo NXP
Description Low-power inverting buffer/line driver
Datasheet 74AUP1G240 Datasheet74AUP1G240 Datasheet (PDF)

www.DataSheet4U.com 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 01 — 6 November 2006 Product data sheet 1. General description The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consump.

  74AUP1G240   74AUP1G240


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www.DataSheet4U.com 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev. 01 — 6 November 2006 Product data sheet 1. General description The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state. This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input OE is HIGH. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-D exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s Input-disable feature allows floating input conditions NXP Semiconductors 74AUP1G240 Low-power inverting buffer/line driver; 3-state s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP1G240GW 74AUP1G240GM 74AUP1G240GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C TSSOP5 XSON6 XSON6 Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm Version SOT353-1 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Marking code p2 p2 p2 Type number 74AUP1G240GW 74AUP1G240GM 74AUP1G240GF 5. Functional diagram 2 1 A OE Y 4 2 4 1 OE A OE Y 001aac528 001aac527 001aac526 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 74AUP1G240_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 6 November 2006 2 of 19 NXP Semiconductors 74AUP1G240 Low-power inverting buffer/line driver; 3-state 6. Pinning information 6.1 Pinning 74AUP1G240 74AUP1G240 OE A 1 2 GND GND 3 001aac525 OE 5 VCC 1 6 VCC OE A 74AUP1G240 1 2 3 6 5 4 VCC n.c. Y A 2 5 n.c. 3 4 Y GND 4 Y 001aac539 001aaf549 Transparent top view Transparent top view Fig 4. Pin configuration SOT353-1 (TSSOP5) Fig 5. Pin configuration SOT886 (XSON6) Fig 6. Pin configuration SOT891 (XSON6) 6.2 Pin description Table 3. Symbol OE A GND Y n.c. VCC Pin description Pin TSSOP5 1 2 3 4 5 XSON6 1 2 3 4 5 6 output enable input data input A ground (0 V) data output Y not connected supply voltage Description 7. Functional description Table 4. Input OE L L H [1] H = HIGH voltage level; L = LOW voltage level; X = Don’t care; Z = high-impedance OFF-state. Function table[1] Output A L H X Y H L Z 74AUP1G240_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 6 November 2006 3 of 19 NXP Semiconductors 74AUP1G240 Low-power inverting buffer/line driver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −0.5 [1] Max +4.6 −50 +4.6 ±50 +4.6 ±20 50 −50 +150 250 Unit V mA V mA V mA mA mA °C mW VO > VCC or VO < 0 V Active mode and Power-down mode VO = 0 V to VCC −0.5 −65 Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Symbol VCC VI VO Tamb ∆t/∆V Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temp.


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