Document
LPC3180
16/32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interface
Rev. 02 — 15 February 2007
Preliminary data sheet
1. General description
The LPC3180 is an ARM9-based microcontroller for embedded applications requiring high performance combined with low power dissipation. It achieves these objectives through the combination of NXP’s state-of-the-art 90 nanometer technology with an ARM926EJ-S CPU core with a Vector Floating Point (VFP) coprocessor and a large array of standard peripherals including USB On-The-Go.
The microcontroller can operate at over 200 MHz CPU frequency (about 220 MIPS per ARM Inc.). The ARM926EJ-S CPU incorporates a 5-stage pipeline and has a Harvard architecture with separate 32 kB instruction and data caches, a demand paged MMU, DSP instruction extensions with a single cycle MAC, and Jazelle Java bytecode execution hardware. A block diagram of the microcontroller is shown in Figure 1.
Power optimization in this microcontroller is done through process and technology development (Intrinsic Power), and architectural means (Managed Power).
The LPC3180 also incorporates an SDRAM interface, NAND flash interfaces, USB 2.0 full-speed interface, seven UARTs, two I2C-bus interfaces, two SPI ports, a Secure Digital (SD) interface, and a 10-bit ADC in addition to many other features.
2. Features
2.1 Key features
I ARM926EJ-S processor with 32 kB instruction cache and 32 kB data cache, running at up to 208 MHz.
I 64 kB of SRAM. I High-performance multi-layer AHB bus system provides a separate bus for CPU data
and instruction fetch, two data buses for the DMA controller, and another for the USB controller. I External memory interfaces: one supports DDR and SDR SDRAM, another supports single-level and multi-level NAND flash devices and can serve as an 8-bit parallel interface. I General purpose DMA controller that can be used with the SD card and SPI interfaces, as well as for memory-to-memory transfers. I USB 2.0 full-speed device, host (OHCI compliant), and OTG block. A dedicated PLL provides the 48 MHz USB clock. I Multiple serial interfaces, including seven UARTs, two SPI controllers, and two single master I2C-bus interfaces. I SD memory card interface.
NXP Semiconductors
LPC3180
16/32-bit ARM microcontroller with external memory interface
I Up to 55 GPI, GPO, and GPIO pins. Includes 12 GPI pins, 24 GPO pins, and six GPIO pins.
I 10-bit ADC with input multiplexing from three pins. I Real-Time Clock (RTC) with separate power supply and power domain, clocked by a
dedicated 32 kHz oscillator. Includes a 128 byte scratch pad memory. The RTC may remain active when the rest of the chip is not powered.
I 32-bit general purpose high-speed timer with 16-bit pre-scaler with capture and compare capability.
I 32-bit millisecond timer driven from the RTC clock. Interrupts may be generated using two match registers.
I Watchdog timer. I Two PWM blocks with an output rate up to 50 kHz. I Keyboard scanner function provides automatic scanning of up to an 8 × 8 key matrix. I Standard ARM test/debug interface for compatibility with existing tools. I Emulation trace buffer with 2 k × 24-bit RAM allows trace via JTAG. I On-chip crystal oscillator. I Stop mode saves power, while allowing many peripheral functions to restart CPU
activity.
I On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal.
I Boundary scan for simplified board testing.
3. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
LPC3180FEL320[1] LFBGA320 plastic low profile fine-pitch ball grid array package; 320 balls; body 13 × 13 × 0.9 mm
[1] F = −40 °C to +85 °C temperature range.
Version SOT824-1
LPC3180_2
Preliminary data sheet
Rev. 02 — 15 February 2007
© NXP B.V. 2007. All rights reserved.
2 of 36
NXP Semiconductors
4. Block diagram
LPC3180
16/32-bit ARM microcontroller with external memory interface
VFP9
ETB ETM9
D-TCM 0 kB
D-CACHE 32 kB
D-SIDE CTRL DATA
ARM 9EJS
MMU
master layer 0
I-TCM 0 kB
I-CACHE 32 kB
I-SIDE CTRL INSTR
1
slave port 0 slave port 1 slave port 2
slave port 3
slave port 5
slave port 6
slave port 7
32 bit, 104 MHz AHB matrix
USB transceiver interface
DMA CTRL PL080 MM 01
23
USB-OTG AHB
MASTER
32 bit, 104 MHz
AHB
GX175 SDRAM CTRL
PORT 2 PORT 3 PORT 4 PORT 0
32 bit wide external memory
SRAM ROM 64 kB 16 kB
AHB slaves
NAND MLC NAND
CTRL
CTRL
AHB2-APB
APB slaves
SPI SD ×2 CARD
AHB slaves
DMA USB SDRAM ETB REGS CONFIG CONFIG REGS
AHB2-APB
APB slaves
I2C UART ×2 ×4
= master/slave connection supported by matrix
Fig 1. Block diagram
FAB slaves
PWM
RTC
SYSTEM CTRL
AHB-
2-FAB
GPIO
WATCHDOG TIMER
HIGH SPEED TIMER
KEY SCAN
INTERRUPT CONTROLLER ×3
DEBUG
MILLISECOND HIGH SPEED 10-BIT
TIMER
UART ×3 ADC
002aac162
LPC3180_2
Preliminary data sheet
Rev. 02 — 15 February 2007
© NXP B.V. 2007. All rights reserved.
3 of 36
NXP Semiconductors
LPC3180.