16/32-bit ARM microcontroller with external memory interface
6.3 AHB matrix
The microcontroller has a multi-layer AHB matrix for inter-block communication. AHB is
the ARM high-speed bus, which is part of the ARM bus architecture. AHB is a
high-bandwidth low-latency bus that supports multi-master arbitration and a bus
grant/request mechanism. For systems where there is only one bus master (the CPU), or
where there are two masters (CPU and DMA) and the CPU does not generally need to
contend with the DMA for program memory access (because the CPU has access to
memory on its local bus or has caches or another AHB bus etc.), this arrangement works
well. However, if there are multiple bus masters and the CPU needs access to external
memory, a single AHB bus can cause a bottleneck. ARM’s solution to this was to invent a
multi-layer AHB which replaces the request/grant and arbitration mechanism with a
multiplexer fabric that pushes arbitration to the level of the devices. Thus, if a CPU and a
DMA controller want access to the same memory, the multi-layer fabric will arbitrate
between the two on granting access to that memory. This allows simultaneous access by
bus masters to different resources at the cost of increased arbitration complexity. As with
all trade-offs, the pros and cons must be analyzed, for a microcontroller operating at
200 MHz, removing guaranteed central arbitration in case more than one bus master is
active in favor of occasional local arbitration gives better performance.
The blocks outside the CPU can be roughly split into memory controllers, serial
communication, I/O, timers/counters and RTC, system control, and debug and trace
blocks. These are described as follows.
6.4 On-chip SRAM
On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed
as 8/16/32 bit. The LPC3180 provides 64 kB of SRAM.
6.5 Memory map
The LPC3180 memory map incorporates several distinct regions, as shown in Figure 3.
When an application is running, the CPU interrupt vectors are re-mapped to allow them to
reside in on-chip SRAM.
Preliminary data sheet
Rev. 02 — 15 February 2007
© NXP B.V. 2007. All rights reserved.
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