16/32-bit ARM microcontroller with external memory interface
• Uses 32 kHz RTC clock
6.12 USB interface
The LPC3180 supports USB in either device, host, or OTG conﬁguration.
6.12.1 USB device controller
The USB device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of register interface, serial interface engine, endpoint buffer memory and DMA
controller. The serial interface engine decodes the USB data stream and writes data to the
appropriate end point buffer memory. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. The
DMA controller when enabled transfers data between the endpoint buffer and the USB
• Fully compliant with USB 2.0 full-speed speciﬁcation.
• Supports 32 physical (16 logical) endpoints.
• Supports control, bulk, interrupt and isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint maximum packet size selection (up to USB maximum speciﬁcation) by
software at run time.
• RAM message buffer size based on endpoint realization and maximum packet size.
• Supports bus-powered capability with low suspend current.
• Supports DMA transfer on all non-control endpoints.
• One duplex DMA channel serves all endpoints.
• Allows dynamic switching between CPU controlled and DMA modes.
• Double buffer implementation for bulk and isochronous endpoints.
6.12.2 USB host controller
The host controller enables data exchange with various USB devices attached to the bus.
It consists of register interface, serial interface engine and DMA controller. The register
interface complies to the OHCI speciﬁcation.
• OHCI compliant.
• OHCI speciﬁes the operation and interface of the USB host controller and SW driver.
• The host controller has four USB states visible to the SW driver:
– USBOperational: Process lists and generate SOF tokens.
– USBReset: Forces reset signaling on the bus, SOF disabled.
– USBSuspend: Monitor USB for wake-up activity.
– USBResume: Forces resume signaling on the bus.
• HCCA register points to interrupt and isochronous descriptors list.
• ControlHeadED and BulkHeadED registers point to control and bulk descriptors list.
Preliminary data sheet
Rev. 02 — 15 February 2007
© NXP B.V. 2007. All rights reserved.
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