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PCA9519

NXP

4-channel level translating I2C-bus/SMBus repeater

PCA9519 4-channel level translating I2C-bus/SMBus repeater Rev. 3 — 10 January 2013 Product data sheet 1. General de...


NXP

PCA9519

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Description
PCA9519 4-channel level translating I2C-bus/SMBus repeater Rev. 3 — 10 January 2013 Product data sheet 1. General description The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables the processor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBus maximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins are over-voltage tolerant and are high-impedance when the PCA9519 is unpowered. The port B drivers are compliant with SMBus I/O levels, while port A uses a current sensing mechanism to detect the input or output LOW signal which prevents bus lock-up. The port A uses a 1 mA current source for pull-up and a 200  pull-down driver. This results in a LOW on port A accommodating smaller voltage swings. The output pull-down on the port A internal buffer LOW is set for approximately 0.2 V, while the input threshold of the internal buffer is set about 50 mV lower than that of the output voltage LOW. When the port A I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a lock-up condition from occurring. The output pull-down on the port B drives a hard LOW and the input level is set at 0.3 of SMBus or I2C-bus vo...




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