CS91

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS06-20208-3E Semicustom CMOS Standard cell array CS91 Series ■ DESCRIPTION The CS91 series 0.11 µm CMOS standard cell is a line of highly integrated CMOS ASICs featuring high speed and low power consumption. This series incorporates up to 48 million gates which have a gate delay time of 16 ps, resulting in both integration and speed about three times higher than conventional products. ■ FEATURES Technology : 0.11 µm silicon-gate CMOS, 5- to 8-layer wiring (Copper is used as wire material.) , Low-K (2.7) Inter-layer material (Inter-layer material that has low permittivity) Support for high speed, high integration, low leak internal cell set. Capable of incorporating on the same chip. Supply voltage : +1.2 V ± 0.1 V (standard specification) Junction temperature range : −40 °C to +125 °C Gate delay time : tpd = 16 ps (1.2 V, inverter, F/O = 1) Gate power consumption : Pd = 6.6 nW/MHz/BC (1.2 V, inverter, F/O = 1) Support for ultra high speed (622 Mbps to 780 Mbps, 2.5 Gbps to 3.125 Gbps, 10 Gbps) interface macros for transmission Special interfaces* : P-CML, LVDS, PCI, SSTL, HSTL, T-LVTTL, and others. Buffer cell dedicated to crystal oscillator IP macros* : CPU (ARM9, ARM7TDMI) , DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, and others. Compiled cells (RAM/ROM/multiplier, and others.) Uses industry standard tools and supports the optimum tools for the application Short-term development ...