HY5DU283222Q

www.DataSheet4U.com HY5DU283222Q 128M(4Mx32) GDDR SDRAM HY5DU283222Q This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2/Oct. 02 1 HY5DU283222Q Revision History No. History 1) Changed some AC parameters a) tAC : Changed from 0.7ns to 0.9ns b) tDQSCK : Changed from 0.6ns to 0.7ns c) tRCD/tRP : Changed from 4clks to 5clks at 222MHz and from 3clks to 4clks at 200/183MHz 1) 2) 3) 4) 0.5 Removed 166MHz part from speed bin Defined IDD specification Defined AC parameters of 250MHz part Changed Pin Capacitance a) Input Clock capacitance : Changed from 2/3pF to 1.7/2.7pF (min/max) b) All other Input-only pins capacitance : Changed from 2/3pF to 1.7/2.7pF (min/max) c) Input/Output capacitance (DQ, DQS, DM) : Changed from 4/5pF to 3.7/4.7pF (min/max) 5) Changed some AC parameters a) tIS/tIH : Changed from 0.9ns to 1.0ns b) tDS/tDH : Changed from 0.45ns to 0.5ns 6) Changed VIH/VIL from Vref +/- 0.31V to Vref +/- 0.35V 1) Changed VIH/VIL from Vref +/- 0.35V to Vref +/- 0.45V 2) Change tCK_max from 5.5ns to 6ns at 250/222MHz and from 10ns to 7ns at 200/183MHz 1) Changed some AC parameters a) tQHS : Changed from 0.75ns to 0.45ns at 200/183MHz b) tDS/tDH : Changed from 0.5ns to 0.45ns 1) tRCD/tRP of 3clocks at 183/200MHz at single bank operation defined 2) tCK Max of 200/183MHz part changed from 7ns to 8ns 1) Power dissipation S...