STATIC RAM. IC62C1024 Datasheet

IC62C1024 Datasheet PDF, Equivalent


Part Number

IC62C1024

Description

128K X 8 HIGH SPEED CMOS STATIC RAM

Manufacture

ICSI

Total Page 8 Pages
PDF Download
Download IC62C1024 Datasheet PDF


IC62C1024 Datasheet
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128K x 8 HIGH-SPEED CMOS STATIC RAM
.EATURES
• High-speed access time: 35, 45, 55, 70 ns
• Low active power: 450 mW (typical)
• Low standby power: 500 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• .ully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
DESCRIPTION
The 1+51 IC62C1024 is a low power,131,072-word by 8-bit
CMOS static RAM. It is fabricated using 1+51's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields higher
performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IC62C1024 is available in 32-pin 600mil DIP, 450mil SOP
and 8*20mm TSOP-1 packages.
.UNCTIONAL BLOCK DIAGRAM
A0-A16
VCC
GND
I/O0-I/O7
DECODER
I/O
DATA
CIRCUIT
512 x 2048
MEMORY ARRAY
COLUMN I/O
CE1
CE2 CONTROL
OE CIRCUIT
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
ALSR005-0A
1

IC62C1024 Datasheet
1+$ + "
PIN CON.IGURATION
32-Pin SOP and DIP
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
PIN CON.IGURATION
32-Pin 8x20mm TSOP-1
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN DESCRIPTIONS
A0-A16
Address Inputs
CE1
Chip Enable 1 Input
CE2
Chip Enable 2 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7
Input/Output
Vcc Power
GND
Ground
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
5V ± 10%
5V ± 10%
TRUTH TABLE
Mode
WE
Not Selected
(Power-down)
Output Disabled
Read
Write
X
X
H
H
L
CE1
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
I/O Operation
High-Z
High-Z
High-Z
DOUT
DIN
Vcc Current
ISB, ISB
ISB, ISB
ICC
ICC
ICC
32 OE
31 A10
30 CE1
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
2 Integrated Circuit Solution Inc.
ALSR005-0A


Features Datasheet pdf www.DataSheet4U.com 1+$ + " 1+$ + " .EATURES 128K x 8 HIGH-SPEED CMOS ST ATIC RAM • High-speed access time: 35, 45, 55, 70 ns • Low active power: 450 mW (typical) • Low standby power: 500 µW (typical) CMOS standby • Output E nable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications .ully static operation: no clock or r efresh required • TTL compatible input s and outputs • Single 5V (±10%) powe r supply DESCRIPTION The 1+51 IC62C102 4 is a low power,131,072-word by 8-bit CMOS static RAM. It is fabricated using 1+51 's highperformance CMOS technolog y. This highly reliable process coupled with innovative circuit design techniq ues, yields higher performance and low power consumption devices. When CE1 is HIGH or CE2 is LOW (deselected), the d evice assumes a standby mode at which t he power dissipation can be reduced by using CMOS input levels. Easy memory ex pansion is provided by using two Chip E nable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls bot.
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