CRD5381 Datasheet: Audio A/D Converter w/ Asynchronous Decimation Filter Reference Design





CRD5381 Audio A/D Converter w/ Asynchronous Decimation Filter Reference Design Datasheet

Part Number CRD5381
Description Audio A/D Converter w/ Asynchronous Decimation Filter Reference Design
Manufacture Cirrus Logic
Total Page 24 Pages
PDF Download Download CRD5381 Datasheet PDF

Features: www.DataSheet4U.com CRD5381 Audio A/D C onverter w/ Asynchronous Decimation Fil ter Reference Design Features Analog Pe rformance  Advanced Multi-bit Delta-s igma Architecture  24-bit Conversion  120 dB Dynamic Range  -110 dB THD+ N  Performance insensitivity to Input Clock Jitter     System Featu res  Output Sample Rate Determined by Input Digital Filter Characteristics  125 dB Stop-band Rejection  Phase- Matched Outputs  Word, Left/Right, or Fsync Clock No External Master Clock Required Easily Scalable for Additiona l Channels Sample Rates from 27 kHz to 192 kHz Four-Channel Time-Division Mult iplexed Output Two Independent Stereo, Left-Justified Outputs LEFT RIGHT CS 5381 A Quad Speed Slave Mode SDOUT SD IN CS8421 A Master Input Slave Ouput SDOUT 2 2 TDM ENABLE Differential An alog Inputs 1-4 SDOUT A PCM Data Ouput / Serial Clock Input Header, J4 LRCK IN PUT SCLK INPUT TDM/SDOUT B 2 2 TDM IN LEFT RIGHT CS5381 B Quad Speed Slave Mode SDOUT SDIN CS8421 B Master .

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CRD5381
Audio A/D Converter w/ Asynchronous Decimation Filter
Reference Design
Features
Analog Performance
 Advanced Multi-bit Delta-sigma Architecture
 24-bit Conversion
 120 dB Dynamic Range
 -110 dB THD+N
 Performance insensitivity to Input Clock Jitter
Digital Filter Characteristics
 125 dB Stop-band Rejection
 Phase-Matched Outputs
System Features
 Output Sample Rate Determined by Input
Word, Left/Right, or Fsync Clock
 No External Master Clock Required
 Easily Scalable for Additional Channels
 Sample Rates from 27 kHz to 192 kHz
 Four-Channel Time-Division Multiplexed
Output
 Two Independent Stereo, Left-Justified
Outputs
LEFT
RIGHT
CS5381 A
Quad Speed SDOUT
Slave Mode
CS8421 A
SDIN Master Input SDOUT
Slave Ouput
22
Differential Analog
Inputs 1-4
22
LEFT
RIGHT
CS5381 B
Quad Speed SDOUT
Slave Mode
TDM ENABLE
SDOUT A
TDM/SDOUT B
PCM Data Ouput/
Serial Clock Input
Header, J4
LRCK INPUT SCLK INPUT
TDM IN
CS8421 B
SDIN Master Input SDOUT
Slave Output
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
MAY ‘05
DS563RD1

                    
                    






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