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FS8107E Low Power Phase-Locked Loop IC
the wireless IC company
HiMARK Technology, Inc. reserves the right to change the product described in this datasheet. All information contained in this datasheet is subject to change without prior notice. HiMARK Technology, Inc. assumes no responsibility for the use of any circuits shown in this datasheet.
Description
The FS8107E is a serial data input, phase-locked loop IC with programmable input and reference frequency dividers. When combined with a VCO, the FS8107E becomes the core of a very low power frequency synthesizer well-suited for mobile communication applications such as paging systems. Compared to the FS8100, the FS8107E is housed in a smaller package and also implements a separate pin for stand-by control.
Features
High maximum input operating frequency — 100 MHz at VDD1 = 1.0 V Up to 22 MHz internal crystal oscillator reference frequency at VDD1 = 1.0 V Extremely low current consumption (IDD,total typically 0.4 mA at fFIN = 90 MHz) 16-bit programmable input frequency divider (including a ÷ 32/33 prescaler) with divide ratio range from 992 to 65535 13-bit programmable reference frequency divider (including a ÷ 8 prescaler) with divide ratio range from 40 to 65528 Optional lock detector output Charge pump output for passive low-pass filter Quick-lock signal output for faster locking Separate pin for stand-by control TSSOP 16L package (0.65mm pitch)
Applications
Pager Wireless communication system
Page 1
June 2001
FS8107E
the wireless IC company
Package and Pin Assignment: 16L, TSSOP
XIN XOUT VDD2 DB DO VSS FIN VDD1
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
TEST NC OPR LE DATA CLK LD NC
HiMARK FS8107E
Dimensions in mm Symbols MIN. A A1 A2 b C D E E1 e L y θ --0.05 0.80 0.19 0.09 4.90 --4.30 --0.45 --0° NOM. ----1.00 ----5.00 6.40 4.40 0.65 0.60 ----MAX. 1.20 0.15 1.05 0.30 0.20 5.10 --4.50 --0.75 0.10 8° MIN. --0.002 0.031 0.007 0.004 0.193 --0.169 --0.018 --0°
Dimensions in inch NOM. ----0.039 ----0.197 0.252 0.173 0.026 0.024 ----MAX. 0.048 0.006 0.041 0.012 0.008 0.201 --0.177 --0.030 0.004 8°
Note: Tolerance + 0.1mm unless otherwise specified
Page 2
June 2001
FS8107E
the wireless IC company
Pin Descriptions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name XIN XOUT VDD2 DB DO VSS FIN VDD1 NC LD CLK DATA LE OPR NC TEST I/O I O POWER O O GND I POWER NC O I I I I NC I Description Reference crystal oscillator or external clock input with internally biased amplifier (any external input to XIN must be ac-coupled) Reference crystal oscillator or external clock output Nominal 3.0 V supply voltage Single-ended quick-lock output for faster locking Single-ended charge pump output for passive low pass filter Ground VCO frequency input with internally biased input amplifier (any external input to FIN must be ac-coupled) Nominal 1.0 V supply voltage No connection Lock detector output (high when PLL is locked) Shift register clock input Serial data input Latch enable input Battery-save control input; normal operation when high, stand-by mode when low No connection Test mode control input with internal pull-down resistor
Block Diagram
FIN DATA CLK LE TEST OPR XIN XOUT
÷ 32/33
N-COUNTER N-LATCH
LOCK DETECTOR
LD DO DB
CONTROL LOGIC
SHIFT REGISTER
PFD
CHARGE PUMP QUICKLOCK
R-LATCH ÷8 R-COUNTER
WINDOW GENERATOR
Page 3
June 2001
FS8107E
the wireless IC company
Absolute Maximum Ratings
VSS = 0 V
Parameter Supply voltage VDD2 Input voltage range Operating temperature range Storage temperature range Soldering temperature range Soldering time range VFIN TOPR TSTG TSLD tSLD VSS – 0.3 to VSS + 7.0 VSS – 0.3 to VDD + 0.3 –10 to 60 –40 to 125 255 10 V V
o
Symbol VDD1
Rating VSS – 0.3 to VSS + 2.0
Unit V
C C C
o
o
s
Recommended Operating Conditions
VSS = 0 V
Value Parameter Symbol min. VDD1 Supply voltage range VDD2 Operating temperature TA 2.0 –10 3.0 25 3.3 60 V
o
Unit typ. 1.0 max. 2.0 V 0.95
C
Page 4
June 2001
FS8107E
the wireless IC company
Electrical Characteristics
(VDD1 = 0.95 to 2.0 V, VDD2 = 2.7 to 3.3 V, VSS = 0 V, TA = 0 to 60°C unless otherwise noted)
Value Parameter Symbol Condition min. VDD1 = 1.0 V, OPR=”H”, VFIN = 0.3 Vpk-pk sinusoid, fFIN = 100 MHz, VXIN = 0.3 Vpk-pk sinusoid, fXIN = 12.8 MHz VDD1 = 0 V, OPR=”L” VFIN = 0.3 Vpk-pk sinusoid VFIN = 0.3 Vpk-pk sinusoid VXIN = 0.3 Vpk-pk sinusoid VXIN = 0.3 Vpk-pk sinusoid 0.3 0.3 0.3 1.5 VIL = 0 V VIH = VDD1 VIL = 0 V VIH = VDD1 VOL = 0.4 V VOH = VDD2 – 0.4 V VOL = 0.4 V VOH = VDD2 – 0.4 V 1.0 1.0 0.1 0.1 2 2 2 10 10 60 60 22 7 100 40 typ. max. Unit
Current consumption
IDD,total
0.40
1.10
mA
Standby current consumption (IDD2) FIN max. operating frequency FIN min. operating frequency XIN max. operating frequency XIN min. operating frequency FIN input voltage swing XIN input voltage swing CLK, DATA, LE logic LOW input voltage CLK, DATA, LE logic HIGH input voltage XIN logic LOW input current XIN logic HIGH input current FIN l.