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K4M513233C Dataheets PDF



Part Number K4M513233C
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 4M x 32Bit x 4 Banks Mobile SDRAM
Datasheet K4M513233C DatasheetK4M513233C Datasheet (PDF)

www.DataSheet4U.com K4M513233C - S(D)N/G/L/F 4M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES • 3.0V & 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. .

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www.DataSheet4U.com K4M513233C - S(D)N/G/L/F 4M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES • 3.0V & 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) • DQM for masking. • Auto refresh. • • • • 64ms refresh period (8K cycle). Commercial Temperature Operation (-25°C ~ 70°C). Extended Temperature Operation (-25°C ~ 85°C). 90Balls FBGA ( -SXXX -Pb, -DXXX -Pb Free). Mobile-SDRAM GENERAL DESCRIPTION The K4M513233C is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. ORDERING INFORMATION Part No. K4M513233C-S(D)N/G/L/F75 K4M513233C-S(D)N/G/L/F7L *1 Max Freq. 133MHz(CL=3), 111MHz(CL=2) 133MHz(CL=3), 83MHz(CL=2) Interface LVCMOS Package 90 FBGA Pb (Pb Free) - S(D)N/G : Low Power, Extended Temperature(-25°C ~ 85°C) - S(D)L/F : Low Power, Commercial Temperature(-25°C ~ 70°C) NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. Address configuration Organization 16Mx32 Bank BA0,BA1 Row A0 - A12 Column Address A0 - A8 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. 1 March 2006 K4M513233C - S(D)N/G/L/F FUNCTIONAL BLOCK DIAGRAM Mobile-SDRAM I/O Control LWE Data Input Register Bank Select LDQM 4M x 32 Sense AMP 4M x 32 4M x 32 4M x 32 Refresh Counter Output Buffer Row Decoder Row Buffer DQi Address Register LRAS CLK CKE CLK ADD Column Decoder Col. Buffer LRAS LCBR Latency & Burst Length LCKE LCBR LWE LCAS Programming Register LWCBR LDQM Timing Register CS RAS CAS WE DQM 2 March 2006 K4M513233C - S(D)N/G/L/F Package Dimension and Pin Configuration < Bottom View*1 > E1 9 A B C D E F G D1 H J K L M N P R E Pin Name CLK CS A A1 b CKE A0 ~ A12 D e 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 1 DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 2 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 Mobile-SDRAM < Top View*2 > 90Ball(6x15) FBGA 3 VSS VSSQ DQ25 DQ30 NC A3 A6 A12 A9 NC VSS DQ9 DQ14 VSSQ VSS 7 VDD VDDQ DQ22 DQ17 NC A2 A10 NC BA0 CAS VDD DQ6 DQ1 VDDQ VDD 8 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 CS WE DQ7 DQ5 DQ3 VSSQ DQ0 9 DQ21 DQ19 VDDQ VDDQ VSSQ VDD A1 A11 RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2 Pin Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground [Unit::mm] z BA0 ~ BA1 RAS CAS WE DQM0 ~ DQM3 DQ0 ~ 31 < Top View*2 > #A1 Ball Origin Indicator SAMSUNG Week 3 K4M513233C-XXXX VDD/VSS VDDQ/VSSQ Symbol A A1 E E1 D D1 e b z Min 0.25 10.9 12.9 0.45 - Typ 11.0 6.40 13.0 11.2 0.80 0.50 - Max 1.00 11.1 13.1 0.55 0.10 March 2006 K4M513233C - S(D)N/G/L/F ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 Mobile-SDRAM Unit V V °C W mA -55 ~ +150 1.0 50 NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for E.


IRS2011PBF K4M513233C K6F1616U6A


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