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Product Specification
PE9701
Product Description
Peregrine’s PE9701 is a high-performance integer-N PLL capable of frequency synthesis up to 3.0 GHz. The device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space PLLs. The PE9701 features a 10/11 dual modulus prescaler, counters, and a phase comparator as shown in Figure 1. Counter values are programmable through either a serial or parallel interface and can also be directly hard wired. The PE9701 is optimized for commercial space applications. Single Event Latch up (SEL) is physically impossible and Single Event Upset (SEU) is better than 10-9 errors per bit / day. It is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate, offering excellent RF performance and intrinsic radiation tolerance. Figure 1. Block Diagram 3000 MHz UltraCMOS™ Integer-N PLL Rad Hard for Space Applications Features
• 3.0 GHz operation • ÷10/11 dual modulus prescaler • Internal phase detector with charge
pump
• Serial, parallel or hardwired
programmable
• Ultra-low phase noise • SEU < 10-9 errors / bit-day • 100 Krad (Si) total dose • 44-lead CQFJ
Fin Fin
Prescaler 10/11
Main Counter 13
fp
D(7:0) 8 Sdata Pre_en M(6:0) A(3:0) R(3:0) fr
Primary 20-bit 20 Latch
Secondary 20-bit Latch
20 20
20 16
Phase Detector
PD_U PD_D
Charge Pump
CP
6
6 fc
R Counter
Document No. 70-0035-02 │ www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 13
PE9701
Product Specification
Figure 2. Pin Configurations (Top View)
GND GND GND Enh VDD LD R3 R2 R1 R0 fr
Figure 3. Package Type
44-lead CQFJ
6
D0, M0 D1, M1 D2, M2 D3, M3 VDD VDD S_W R, D4, M4 Sdata, D5, M5 Sclk, D6, M6 FSELS, D7, Pre_en GND
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
fc VDD_fc N/C CP VDD Cext VDD Dout VDD_fp fp GND
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
FSELP, A0 E_WR, A1 M2_WR, A2 Smode, A3 Bmode VDD M1_WR A_WR Hop_WR Fin Fin
Table 1. Pin Descriptions
Pin No.
1 2 3 4 5 6 7 M0 8 D1 M1 9 D2 M2 10 D3 M3 11 12 VDD VDD S_WR 13 D4 M4 Parallel Direct Input Input Direct Parallel Direct Parallel Direct Parallel Direct ALL ALL Serial Input Input Input Input Input Input Input (Note 1) (Note 1) Input M Counter bit0 (LSB). Parallel data bus bit1. M Counter bit1. Parallel data bus bit2. M Counter bit2. Parallel data bus bit3. M Counter bit3. Same as pin 1. Same as pin 1. Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data is transferred to the secondary register on S_WR or Hop_WR rising edge. Parallel data bus bit4 M Counter bit4 Document No. 70-0035-02 │ UltraCMOS™ RFIC Solutions
Pin Name
VDD R0 R1 R2 R3 GND D0
Interface Mode
ALL Direct Direct Direct Direct ALL Parallel
Type
(Note 1) Input Input Input Input (Note 1) Input
Desc.