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HOTLink Transceiver. CY7C924ADX Datasheet

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HOTLink Transceiver. CY7C924ADX Datasheet






CY7C924ADX Transceiver. Datasheet pdf. Equivalent




CY7C924ADX Transceiver. Datasheet pdf. Equivalent





Part

CY7C924ADX

Description

200-MBaud HOTLink Transceiver



Feature


CY7C924ADX 200 MBaud HOTLink® Transceiv er 200 MBaud HOTLink® Transceiver Fea tures ■ Second generation HOTLink® t echnology ■ Fibre channel and ESCON® compliant 8B/10B encoder/decoder ■ 1 0 or 12-bit preencoded data path (raw m ode) ■ 8 or 10-bit encoded data trans port (using 8B/10B coding) ■ Synchron ous or asynchronous TTL parallel interf ace ■ UTOPIA compatible host bus.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C924ADX Datasheet


Cypress Semiconductor CY7C924ADX

CY7C924ADX; interface ■ Embedded/bypassable 256-c haracter synchronous FIFOs ■ Integrat ed support for daisy-chain and ring top ologies ■ Domain or individual destin ation device addressing ■ 50 to 200 M Baud serial signaling rate ■ Internal PLLs with no external PLL components Dual differential PECL compatible se rial inputs ■ Dual differential PECL compatible serial outputs ■ Comp.


Cypress Semiconductor CY7C924ADX

atible with fiber optic modules and copp er cables ■ Built-in self-test (BIST) for link testing ■ Link quality indi cator ■ Single +5.0 V ±10% supply 100-pin TQFP sponding CY7C924ADX par ts. As a second generation HOTLink devi ce, the CY7C924ADX provides enhanced le vels of technology, functionality, and integration over the field proven CY7B9 23/933 HOTLink. The transmi.


Cypress Semiconductor CY7C924ADX

t section of the CY7C924ADX HOTLink can be configured to accept either 8 or 10 bit data characters on each clock cycle , and stores the parallel data in an in ternal Transmit FIFO. Data is read from the Transmit FIFO and is encoded using an embedded 8B/10B encoder to improve its serial transmission characteristics . These encoded characters are then ser ialized and output.

Part

CY7C924ADX

Description

200-MBaud HOTLink Transceiver



Feature


CY7C924ADX 200 MBaud HOTLink® Transceiv er 200 MBaud HOTLink® Transceiver Fea tures ■ Second generation HOTLink® t echnology ■ Fibre channel and ESCON® compliant 8B/10B encoder/decoder ■ 1 0 or 12-bit preencoded data path (raw m ode) ■ 8 or 10-bit encoded data trans port (using 8B/10B coding) ■ Synchron ous or asynchronous TTL parallel interf ace ■ UTOPIA compatible host bus.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C924ADX Datasheet




 CY7C924ADX
CY7C924ADX
200 MBaud HOTLink® Transceiver
200 MBaud HOTLink® Transceiver
Features
Second generation HOTLink® technology
Fibre channel and ESCON® compliant 8B/10B
encoder/decoder
10 or 12-bit preencoded data path (raw mode)
8 or 10-bit encoded data transport (using 8B/10B coding)
Synchronous or asynchronous TTL parallel interface
UTOPIA compatible host bus interface
Embedded/bypassable 256-character synchronous FIFOs
Integrated support for daisy-chain and ring topologies
Domain or individual destination device addressing
50 to 200 MBaud serial signaling rate
Internal PLLs with no external PLL components
Dual differential PECL compatible serial inputs
Dual differential PECL compatible serial outputs
Compatible with fiber optic modules and copper cables
Built-in self-test (BIST) for link testing
Link quality indicator
Single +5.0 V ±10% supply
100-pin TQFP
sponding CY7C924ADX parts. As a second generation HOTLink
device, the CY7C924ADX provides enhanced levels of
technology, functionality, and integration over the field proven
CY7B923/933 HOTLink.
The transmit section of the CY7C924ADX HOTLink can be
configured to accept either 8 or 10 bit data characters on each
clock cycle, and stores the parallel data in an internal Transmit
FIFO. Data is read from the Transmit FIFO and is encoded using
an embedded 8B/10B encoder to improve its serial transmission
characteristics. These encoded characters are then serialized
and output from two Positive ECL (PECL) compatible differential
transmission line drivers at a bit rate of 10 or 12 times the
character rate.
The receive section of the CY7C924ADX HOTLink accepts a
serial bit stream from one of two PECL compatible differential
line receivers and, using a completely integrated PLL Clock
Synchronizer, recovers the timing information necessary for data
reconstruction. The recovered bit stream is deserialized and
framed into characters, 8B/10B decoded, and checked for trans-
mission errors. Recovered decoded characters are recon-
structed into either 8 or 10 bit data characters, written to an
internal Receive FIFO, and presented to the destination host
system.
Systems that present externally encoded or scrambled data at
the parallel interface may bypass the integrated 8B/10B
encoder/decoder. The embedded FIFOs may also be bypassed
to create a reference locked serial transmission link. For those
systems requiring even greater FIFO storage capability, external
FIFOs may directly couple to the CY7C924ADX device through
the parallel interface without additional glue-logic.
0.35 µ CMOS technology
Pb-free package available
Functional Description
The 200 MBaud CY7C924ADX HOTLink Transceiver is a
point-to-point communications building block allowing the
transfer of data over high speed serial links (optical fiber,
balanced, and unbalanced copper transmission lines) at speeds
ranging between 50 and 200 MBaud. The transmit section
accepts parallel data of selectable width and converts it to serial
data, while the receiver section accepts serial data and converts
it to parallel data of selectable width. Figure 1 illustrates typical
connections between two independent host systems and corre-
You can configure the TTL parallel I/O interface as either a FIFO
(configurable for UTOPIA emulation or for depth expansion
through external FIFOs) or as a pipeline register extender. The
FIFO configurations are optimized for transport of
time-independent (asynchronous) 8 or 10 bit character oriented
data across a link. A Built-In Self-Test (BIST) pattern generator
and checker permits at-speed testing of the high speed serial
data paths in both the transmit and receive sections, and across
the interconnecting links. HOTLink devices are ideal for a variety
of applications where parallel interfaces can be replaced with
high speed, point-to-point serial links. Some applications include
interconnecting workstations, backplanes, servers, mass
storage, and video transmission equipment.
Figure 1. HOTLink System Connections
Data
Receive
Serial Link
Transmit
Data
Control
Status
Data
Transmit
CY7C924ADX
Serial Link
CY7C924ADX
Control
Status
Receive
Data
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-02008 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 18, 2019




 CY7C924ADX
CY7C924ADX
CY7C924ADX Transceiver Logic Block Diagram
TX
STATUS
3
TXDATA
13
CONTROL TXCLK
MODE REFCLK
11 9
RX
STATUS
4
RXDATA
13
Output Register
Mode
Control
Output Register
RXCLK
Address Register
Input Register
Flags
MUX
Flags
Transmit
FIFO
MUX
Transmit
Formatter
Pipeline Register
Byte-Packer
BIST LFSR
8B/10B Encoder
MUX
Serial Shifter
LOOPBACK
CONTROL
DLB[1:0]
LOOPTX
3
Transmit
PLL Clock
Multiplier
Elasticity
Buffer
Receive
FIFO
MUX
Receive
Formatter
Pipeline Register
Byte-Unpacker
Address Matching
Receive
Control
State
Machine
BIST LFSR
8B/10B Decoder
Transmit
Control
State
Machine
Bit Clock
Deserializer
Framer
Clock
Divider
Receive
Clock/Data
Recovery
Bit Clock
Routing Matrix
Mode
CONTROL
AM*
TXEN*
RXEN*
TXSTOP*
TXRST*
RXRST*
RFEN
TXBISTEN*
RXBISTEN*
RESET*[1:0]
MODE
RANGESEL
SPDSEL
RXMODE[1:0]
FIFOBYP*
EXTFIFO
ENCBYP*
BYTE8/10*
TEST*
RXSTATUS
LFI*
RXEMPTY*
RXHALF*
RXFULL*
TX STATUS
TXEMPTY*
TXHALF*
TXFULL*
Signal
Validation
LOOPBACK
CONTROL
OUTA
CURSETA
OUTBCURSETB
INA
INB A/B*
CARDET
Document Number: 38-02008 Rev. *J
Page 2 of 71




 CY7C924ADX
CY7C924ADX
Contents
Pin Configuration ............................................................. 4
Pin Descriptions ............................................................... 5
CY7C924ADX HOTLink Operation ................................ 13
Overview ................................................................... 13
Transmit Data Path ................................................... 13
Receive Data Path .................................................... 14
CY7C924ADX HOTLink Transceiver
Block Diagram Description ............................................ 15
Transmit Input/Output Register ................................. 15
Transmit FIFO ........................................................... 15
Transmit Formatter and Validation ............................ 16
Encoder Block ........................................................... 17
Transmit Shifter ......................................................... 18
Routing Matrix ........................................................... 18
Serial Line Drivers ..................................................... 19
Transmit PLL Clock Multiplier .................................... 19
Transmit Control State Machine ................................ 19
Elasticity Buffer .......................................................... 21
Serial Line Receivers ................................................ 21
Signal Detect ............................................................. 21
Clock/Data Recovery ................................................. 21
Clock Divider ............................................................. 21
Deserializer/Framer ................................................... 22
Decoder Block ........................................................... 22
Receive Formatter ..................................................... 22
Receive Control State Machine ................................. 24
Receive FIFO ............................................................ 25
Receive Input Register .............................................. 25
Receive Output Register ........................................... 25
Serial Address Register ............................................. 25
Maximum Ratings ........................................................... 27
Operating Range ............................................................. 27
CY7C924ADX DC Electrical Characteristics ................ 27
Capacitance .................................................................... 29
AC Test Loads and Waveforms ..................................... 29
CY7C924ADX Transmitter TTL
Switching Characteristics, FIFO Enabled .................... 30
CY7C924ADX Receiver TTL Switching Characteristics,
FIFO Enabled .................................................................. 31
CY7C924ADX Transmitter TTL
Switching Characteristics, FIFO Bypassed ................. 31
CY7C924ADX Receiver TTL Switching Characteristics,
FIFO Bypassed ............................................................... 32
CY7C924ADX Receiver Switching Characteristics ..... 33
CY7C924ADX Transmitter
Switching Characteristics .............................................. 33
CY7C924ADX REFCLK Input
Switching Characteristics .............................................. 34
CY7C924ADX HOTLink Transmitter
Switching Waveforms .................................................... 35
CY7C924ADX HOTLink Receiver
Switching Waveforms .................................................... 38
CY7C924ADX HOTLink Transceiver Operation ........... 40
CY7C924ADX HOTLink Transmit-Path
Operating Mode Description ......................................... 41
Synchronous Encoded .............................................. 41
Synchronous Pre-encoded ........................................ 41
Asynchronous Encoded ............................................ 41
Asynchronous Byte-Packed ...................................... 42
Asynchronous Pre-encoded ...................................... 42
CY7C924ADX HOTLink Receive-Path
Operating Mode Descriptions ....................................... 43
Synchronous Decoded .............................................. 43
Synchronous Undecoded .......................................... 43
Asynchronous Decoded ............................................ 43
Asynchronous Byte-Packed ...................................... 44
Asynchronous Undecoded ........................................ 44
BIST Operation and Reporting ...................................... 45
BIST Enable Inputs ................................................... 45
BIST Transmit Path ................................................... 45
BIST Receive Path .................................................... 46
BIST Three-state Control .......................................... 47
Bus Interfacing ............................................................... 47
UTOPIA Interface Background .................................. 47
UTOPIA Address Match and Selection ..................... 47
Address Match and FIFO Flag Access ...................... 47
Device Selection ........................................................ 48
Transmit Data Selection ............................................ 49
Receive Data Selection ............................................. 50
FIFO Reset Address Match ....................................... 51
FIFO Reset Sequence ............................................... 51
Receive FIFO Reset Sequence ................................. 52
Serial Address Register Access ................................ 54
Accessing Serial Address Register ........................... 54
X3.230 Codes and Notation Conventions ................. 54
Notation Conventions ................................................ 55
8B/10B Transmission Code ....................................... 55
Transmission Order ................................................... 55
Valid and Invalid Transmission Characters ............... 55
Use of the Tables
for Generating Transmission Characters .......................... 56
Use of the Tables for Checking the Validity
of Received Transmission Characters .............................. 56
Printed Circuit Board Layout Suggestions .................. 62
Ordering Information ...................................................... 63
Ordering Code Definitions ......................................... 63
Package Diagram ............................................................ 64
Acronyms ........................................................................ 65
Document Conventions ................................................. 65
Units of Measure ....................................................... 65
Document History Page ................................................. 66
Sales, Solutions, and Legal Information ...................... 71
Worldwide Sales and Design Support ....................... 71
Products .................................................................... 71
PSoC® Solutions ...................................................... 71
Cypress Developer Community ................................. 71
Technical Support ..................................................... 71
Document Number: 38-02008 Rev. *J
Page 3 of 71






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