SDA2546-5

www.DataSheet4U.com Nonvolatile Memory 4-Kbit E2PROM with I2C Bus Interface SDA 2546-5 Preliminary Data MOS IC Features q Word-organized reprogrammable nonvolatile memory q q q q q q q q in n-channel floating-gate technology (E2PROM) 512 × 8-bit organization Supply voltage 5 V Serial 2-line bus for data input and output (I2C Bus) Reprogramming mode, 10 ms erase/write cycle Reprogramming by means of on-chip control (without external control) The end of the programming cycle can be checked Data retention in excess of 10 years More than 104 reprogramming cycles per address P-DIP-8-1 Type SDA 2546-5 Ordering Code Q67100-H5096 Package P-DIP-8-1 Circuit Description I2C Bus Interface The I2C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits. It consists of a data line SDA and a clock line SCL. The data line requires an external pull-up resistor to VCC (open drain output stages). The possible operational states of the I2C Bus are shown in figure 1. In the quiescent state, both lines SDA and SCL are high, i.e. the output states are disabled. As long as SCL remains "1", information changes on the data bus indicate the start or the end of a data transfer between two components. The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" a stop condition. During a data transfer the information on the data bus will only change when the clock line SCL is "0". The information on SDA is valid as long as SC...