PZ3032

www.DataSheet4U.com INTEGRATED CIRCUITS PZ3032 32 macrocell CPLD Product specification IC27 Data Handbook 1997 Feb 20 Philips Semiconductors Philips Semiconductors Product specification 32 macrocell CPLD PZ3032 FEATURES Industry’s first TotalCMOS™ PLD – both CMOS design and Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed process technologies DESCRIPTION The PZ3032 CPLD (Complex Programmable Logic Device) is the first in a family of Fast Zero Power (FZP™) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZP™ design technique, the PZ3032 offers true pin-to-pin speeds of 8ns, while simultaneously delivering power that is less than 35µA at standby without the need for ‘turbo bits’ or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD – 70% lower at 50MHz. These devices are the first TotalCMOS™ PLDs, as they use both a CMOS process technology and the patented full CMOS FZP™ design technique. For 5V applications, Philips also offers the high speed PZ5032 CPLD that offers pin-to-pin speeds of 6ns. The Philips FZP™ CPLDs introduce the new patent-pending XPLA™ (eXtended Programmable Logic Array) architecture. The XPLA™ architecture combines t...