PZ3064

www.DataSheet4U.com INTEGRATED CIRCUITS PZ3064 64 macrocell CPLD Product specification IC27 Data Handbook 1997 Mar 05 Philips Semiconductors Philips Semiconductors Product specification 64 macrocell CPLD PZ3064 FEATURES Industry’s first TotalCMOS™ PLD – both CMOS design and Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed process technologies DESCRIPTION The PZ3064 CPLD (Complex Programmable Logic Device) is the second in a family of Fast Zero Power (FZP™) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 64 macrocell CPLD. With the FZP™ design technique, the PZ3064 offers true pin-to-pin speeds of 10ns, while simultaneously delivering power that is less than 50µA at standby without the need for ‘turbo bits’ or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD – 70% lower at 50MHz. These devices are the first TotalCMOS™ PLDs, as they use both a CMOS process technology and the patented full CMOS FZP™ design technique. For 5V applications, Philips also offers the high speed PZ5064 CPLD that offers these features in a full 5V implementation. The Philips FZP™ CPLDs introduce the new patent-pending XPLA™ (eXtended Programmable Logic Array) architecture. The XPLA™ arc...