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IDT70V3569S Dataheets PDF



Part Number IDT70V3569S
Manufacturers IDT
Logo IDT
Description HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Datasheet IDT70V3569S DatasheetIDT70V3569S Datasheet (PDF)

www.DataSheet4U.com HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: x x IDT70V3569S x x x x True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 4.2/5/6ns (max.) – Industrial: 5/6ns (max) Pipelined output mode Counter enable and reset features Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports – .

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www.DataSheet4U.com HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: x x IDT70V3569S x x x x True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 4.2/5/6ns (max.) – Industrial: 5/6ns (max) Pipelined output mode Counter enable and reset features Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports – 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth) – Fast 4.2ns clock to data out – 1.8ns setup to clock and 0.7ns hold on all control, data, and x x x x x address inputs @ 133MHz – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time Separate byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (±150mV) power supply for core LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV) power supply for I/Os and control signals on each port Industrial temperature range (-40°C to +85°C) is available for selected speeds Available in a 208-pin Plastic Quad Flatpack (PQFP), 208-ball fine-pitch Ball Grid Array, and 256-pin Ball Grid Array Functional Block Diagram BE3L BE3R BE2L BE1L BE0L BE2R BE1R BE0R R/WL B W 0 L B W 1 L B W 2 L B B WW 3 3 L R BB WW 2 1 RR B W 0 R R/WR CE0L CE1L CE0R CE1R OEL Dout0-8_L Dout9-17_L Dout18-26_L Dout27-35_L Dout0-8_R Dout9-17_R Dout18-26_R Dout27-35_R OER 16K x 36 MEMORY ARRAY I/O0L- I/O35L Din_L Din_R I/O0R - I/O35R CLKL A13L A0L CNTRSTL ADSL CNTENL CLKR , Counter/ Address Reg. A 13R ADDR_L ADDR_R Counter/ Address Reg. A 0R CNTRSTR ADSR CNTENR 4831 tbl 01 APRIL 2001 1 ©2001 Integrated Device Technology, Inc. DSC 4831/8 IDT70V3569S High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70V3569 is a high-speed 16K x 36 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V3569 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3569 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) remains at 3.3V. Pin Configuration(1,2,3,4) A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 IO19L IO18L B1 B2 VSS B3 NC B4 NC B5 NC B6 A12L B7 A8L B8 BE1L B9 VDD B10 CLKL CNTENL A4L B11 B12 B13 A0L B14 OPTL I/O17L B15 B16 VSS B17 I/O20R C1 VSS I/O18R C2 C3 VSS C4 NC C5 A13L C6 A9L C7 BE2L C8 CE0L C9 VSS C10 ADSL C11 A5L C12 A1L C13 VSS C14 VDDQR I/O16L I/O15R C15 C16 C17 VDDQL I/O19R VDDQR VDD D1 D2 D3 D4 NC D5 NC D6 A10L D7 BE3L D8 CE1L D9 VSS D10 R/WL D11 A6L D12 A2L D13 VDD I/O16R I/O15L D14 D15 D16 VSS D17 I/O22L E1 VSS E2 I/O21L I/O20L E3 E4 NC A11L A7L BE0L VDD OEL CNTRSTL A3L VDD I/O17R VDDQL I/O14L I/O14R E14 E15 E16 E17 I/O23L I/O22R VDDQR I/O21R F1 F2 F3 F4 I/O12L I/O13R F14 F15 VSS F16 I/O13L F17 VDDQL I/O23R I/O24L G1 G2 G3 VSS G4 VSS G14 I/O12R I/O11L VDDQR G15 G16 G17 I/O26L H1 VSS H2 I/O25L I/O24R H3 H4 I/O9L VDDQL I/O10L I/O11R VDD J1 I/O26R VDDQR I/O25R J2 J3 J4 70V3569BF BF-208(5) 208-Pin fpBGA Top View(6) H14 H15 H16 H17 VDD J14 IO9R J15 VSS J16 I/O10R J17 VDDQL K1 VDD K2 VSS K3 VSS K4 VSS K14 VDD K15 VSS VDDQR K16 K17 I/O28R L1 VSS L2 I/O27R L3 VSS L4 I/O7R VDDQL I/O8R L14 L15 L16 VSS L17 I/O29R I/O28L VDDQR I/O27L M1 M2 M3 M4 I/O6R M14 I/O7L M15 VSS M16 I/O8L M17 VDDQL I/O29L I/O30R N1 N2 N3 VSS N4 VSS N14 I/O6L I/O5R VDDQR N15 N16 N17 I/O31L P1 VSS I/O31R I/O30L P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 I/O3R VDDQL I/O4R P14 P15 P16 I/O5L P17 I/O32R I/O32L VDDQR I/O35R R1 R2 R3 R4 NC R5 NC R6 A12R R7 A8R R8 BE1R R9 VDD R10 CLKR CNTEN R A4R R11 R12 R13 I/O2L R14 I/O3L R15 VSS R16 I/O4L R17 VSS T1 I/O33L I/O34R T2 T3 NC T4 NC T5 A13R T6 A9R T7 BE2R CE0R T8 T9 VSS T10 ADSR T11 A5R T12 A1R T13 VSS T14 VDDQL I/O1R VDDQR T15 T16 T17 I/O33R I/O34L VDDQL VSS U1 U2 U3 U4 NC U5 NC U6 A10R U7 BE3R U8 CE1R U9 VSS U10 R/WR A6R U12 A2R U13 VSS U14 I/O0R U15 VSS U16 I/O2R U17 VSS I/O35L VDD NC NC A11R A7R BE0R VDD OER A3R A0R VDD OPTR I/O0L I/O1L , NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that .


HW-300B IDT70V3569S IRFP2907


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