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GS8161E18 Dataheets PDF



Part Number GS8161E18
Manufacturers GSI
Logo GSI
Description (GS8161E18 - GS8161E36) Sync Burst SRAMs
Datasheet GS8161E18 DatasheetGS8161E18 Datasheet (PDF)

www.DataSheet4U.com GS8161E18(T/D)/GS816132(D)/GS816136(T/D) 100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mo.

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www.DataSheet4U.com GS8161E18(T/D)/GS816132(D)/GS816136(T/D) 100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Dual Cycle Deselect (DCD) operation • IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP and 165-bump BGA packages 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. DCD Pipelined Reads The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. Functional Description Applications The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) is a 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order Core and Interface Voltages The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible. Parameter Synopsis -250 Pipeline 3-1-1-1 3.3 V 2.5 V Flow Through 2-1-1-1 3.3 V 2.5 V tKQ tCycle Curr (x18) Curr (x36) Curr (x18) Curr (x36) tKQ tCycle Curr (x18) Curr (x36) Curr (x18) Curr (x36) 2.5 4.0 280 330 275 320 5.5 5.5 175 200 175 200 -225 2.7 4.4 255 300 250 295 6.0 6.0 165 190 165 190 -200 3.0 5.0 230 270 230 265 6.5 6.5 160 180 160 180 -166 3.4 6.0 200 230 195 225 7.0 7.0 150 170 150 170 -150 3.8 6.7 185 215 180 210 7.5 7.5 145 165 145 165 -133 4.0 7.5 165 190 165 185 8.5 8.5 135 150 135 150 Unit ns ns mA mA mA mA ns ns mA mA mA mA Rev: 2.13 11/2004 1/36 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161E18(T/D)/GS816132(D)/GS816136(T/D) GS8161E18 100-Pin TQFP Pinout (Package T) VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 1M X 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A E1 A NC NC BB BA A VDD VSS CK GW BW G ADSC ADSP ADV A A A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC Rev: 2.13 11/2004 LBO A A A A A1 A0 TMS TDI VSS VDD TDO TCK A A A A A A A 2/36 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest doc.


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