GS88136T

www.DataSheet4U.com Preliminary GS88118/36T-11/11.5/100/80/66 100-Pin TQFP Commercial Temp Industrial Temp 1.11 9/2000Features FT pin for user-configurable flow through or pipelined operation Single Cycle Deselect (SCD) Operation IEEE 1149.1 JTAG-compatible Boundary Scan On-chip write parity checking; even or odd selectable 3.3 V +10%/–5% core power supply 2.5 V or 3.3 V I/O supply LBO pin for Linear or Interleaved Burst mode Internal input resistors on mode pins allow floating mode pins Default to Interleaved Pipeline mode Byte Write (BW) and/or Global Write (GW) operation Common data inputs and data outputs Clock Control, registered, address, data, and control Internal self-timed write cycle Automatic power-down for portable applications 100-lead TQFP package -11 -11.5 -100 -80 -66 10 ns 10 ns 12.5 ns 15 ns Pipeline tCycle 10 ns 4.0 ns 4.0 ns 4.0 ns 4.5 ns 5.0 ns 3-1-1-1 tKQ 225 mA 225 mA 225 mA 200 mA 185 mA IDD 11 ns 11.5 ns 12 ns 14 ns 18 ns Flow tKQ 15 ns 15 ns 15 ns 20 ns Through tCycle 15 ns 2-1-1-1 IDD 180 mA 180 mA 180 mA 175 mA 165 mA MHz 512K x 18, 256K x 36 ByteSafe™ 100 MHz–66 3.3 V VDD 8Mb Sync Burst SRAMs 3.3 V and 2.5 V I/O counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can b...