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ZL30116 Dataheets PDF



Part Number ZL30116
Manufacturers Zarlink Semiconductor
Logo Zarlink Semiconductor
Description SONET/SDH Low Jitter System Synchronizer
Datasheet ZL30116 DatasheetZL30116 Datasheet (PDF)

ZL30116 SONET/SDH OC-48/OC-192 System Synchronizer Data Sheet Features • Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64 • Programmable output synthesizers generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in.

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ZL30116 SONET/SDH OC-48/OC-192 System Synchronizer Data Sheet Features • Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64 • Programmable output synthesizers generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz • Provides two DPLLs which are independently configurable through a serial software interface • DPLL1 provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), selectable loop bandwidth and pull-in range • DPLL2 provides a comprehensive set of features necessary for generating derived output clocks and other general purpose clocks • Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz June 2008 Ordering Information ZL30116GGGV2 100 Pin CABGA Trays ZL30116GGG2V2100 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC • Supports master/slave configuration for AdvancedTCATM • Configurable input to output delay and output to output phase alignment • Optional external feedback path provides dynamic input to output delay compensation • Provides 3 sync inputs for output frame pulse alignment • Generates several styles of output frame pulses with selectable pulse width, polarity and frequency • Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities • Supports IEEE 1149.1 JTAG Boundary Scan osco osci ref0 ref1 ref2 ref3 ref4 ref5 ref6 ref7 sync0 sync1 sync2 int_b trst_b tck tdi tms tdo dpll2_ref dpll1_hs_en dpll1_lock dpll1_holdover diff0_en diff1_en Master Clock IEEE 1449.1 JTAG ref7:0 sync2:0 Reference ref_&_sync_status Monitors DPLL2 ref ref DPLL1 sync fb_clk fb_fp P0 Synthesizer P1 Synthesizer SONET/SDH APLL Feedback Synthesizer p0_clk0 p0_clk1 p0_fp0 p0_fp1 p1_clk0 p1_clk1 diff0_p/n diff1_p/n sdh_clk0 sdh_clk1 sdh_fp0 sdh_fp1 fb_clk SPI Interface sck si so cs_b Controller & State Machine rst_b slave_en dpll1_mod_sel1:0 ext_fb_fp ext_fb_clk sdh_filter filter_ref0 filter_ref1 Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005-2008, Zarlink Semiconductor Inc. All Rights Reserved. ZL30116 Applications • AdvancedTCATM Systems • Multi-Service Edge Switches or Routers • Multi-Service Provisioning Platforms (MSPPs) • Add-Drop Multiplexers (ADMs) • Wireless/Wireline Gateways • Wireless Base Stations • DSLAM / Next Gen DLC • Core Routers Data Sheet 2 Zarlink Semiconductor Inc. ZL30116 Data Sheet Table of Contents 1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2 DPLL Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.7 Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.8 External Feedback Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3 Zarlink Semiconductor Inc. ZL30116 Data Sheet List of Figures Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Automatic Mode State Machine . . . . . . . . . . . .


VSC7376 ZL30116 PM7830


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