AC104QF Transceiver Datasheet

AC104QF Datasheet, PDF, Equivalent


Part Number

AC104QF

Description

Ultra Low Power 10/100 Quad RMII Ethernet Transceiver

Manufacture

Altima

Total Page 30 Pages
Datasheet
Download AC104QF Datasheet


AC104QF
www.DataSheet4U.com
Altima Communications Inc.
AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
GENERAL DESCRIPTION
The AC104QF is a highly integrated, 3.3V, low
power, four port, 10Base-T/100Base-TX/FX,
Ethernet transceiver implemented in 0.35µm CMOS
technology. Multiple modes of operation including
normal operation, test mode and power saving mode
are available through either hardware or software
control.
Features include MAC interfaces, ENDECs,
Scrambler/Descrambler, and Auto-Negotiation
(ANeg) with support for parallel detection. The
transmitter includes a dual-speed clock synthesizer
that only needs one external clock source. The chip
has built-in wave shaping driver circuit for both
10Mbps and 100Mbps, eliminating the need for an
external hybrid filter. The receiver has an adaptive
equalizer / DC restoration circuit for accurate clock /
data recovery for the 100Base-TX signal. It also
provides an on-chip low pass filer / Squelch circuit
for the 10Base-T signal.
MAC interfaces support four ports of 10/100 RMII.
Media Interfaces support 4 ports of 10/100TX or 3
ports 10/100TX and 1 port 100FX.
FEATURES
4 RMII
RMII 5Volt tolerant and 2.5Volt capable
4 10/100 TX or 3 10/100 TX and 1 100 FX
Full Duplex or Half Duplex
FEFI on 100FX
Very small package
100PQFP
Very low power – TYP < 280mW (/ port)
Cable Detect mode – TYP < 40mW (/ port)
Power Down mo de – TYP < 3.3mW (/ port)
Selectable TX drivers for 1:1 or 1.25:1
transformers for additional power reduction
3.3Volt .35micron CMOS
Fully compliant with
IEEE 802.3 / 802.3u
RMII
UNH test labs
Baseline Wander Compensation
Multi-Function LED outputs
Cable length indicator
Reverse polarity detection and correction with
Register Bit indication – Automatic or Forced
8 programmable interrupts
Diagnostic registers
BLOCK DIAGRAM
Port 0
Port 1
Port 2
Port 3
RMII/MII
Interface
MII SMI
PCS
.Framer
.Carrier Detect
.4B/5B
PMA
.Clock Recov.
.Link Monitor
.Signal Detect
25
MHz
10BASE -T
Control/Status
20
MHz
TP_PMD
100TX
.MLT-3
.BLW
.Stream Cipher
100RX
10TX
10RX
Mux
TXOP/N(3)
RXIP/N(3)
FXTP/N(3)
FXRP/N(3)
RX FLP
MII Serial Management
Interface and Registers
PLLClk Gen.
Test/LED Control
Auto-
25 Negotiation
MHz
PHYAD[4:0]
XTLP/N CKIN TEST[3:0] LED Drivers
TXOP/N(0)
RXIP/N(0)
TXOP/N(1)
RXIP/N(1)
TXOP/N(2)
RXIP/N(2)

AC104QF
AC104QF
Ultra Low Power 10/100 Quad RMII Ethernet Transceiver
REVISION HISTORY
REVISION# DATE
1.0 July 1998
3.2 June 2000
4.0 Sept 12, 2000
CHANGE BY
xx
xx
Helene
CHANGE DESCRIPTION
Preliminary Release
Final Release
1. Change the default value of register 3 [15:0] =
101010101000001 on page 20
2. Enhance the descriptions of the DPLX and SPEED (register
18.11 and 18.10) on page 24
2055 Gateway Parkway Suite 700, San Jose, CA 95110 (408) 453-3700 (www.altimacom.com)
Altima Communications Inc. reserves the right to make changes to this document without notice.
Document Revision 4.0
Page 2 of 37


Features www.DataSheet4U.com Altima Communicatio ns Inc. AC104QF Ultra Low Power 10/100 Quad RMII Ethernet Transceiver GENERAL DESCRIPTION The AC104QF is a highly int egrated, 3.3V, low power, four port, 10 Base-T/100Base-TX/FX, Ethernet transcei ver implemented in 0.35µm CMOS technol ogy. Multiple modes of operation includ ing normal operation, test mode and pow er saving mode are available through ei ther hardware or software control. Feat ures include MAC interfaces, ENDECs, Sc rambler/Descrambler, and Auto-Negotiati on (ANeg) with support for parallel det ection. The transmitter includes a dual -speed clock synthesizer that only need s one external clock source. The chip h as built-in wave shaping driver circuit for both 10Mbps and 100Mbps, eliminati ng the need for an external hybrid filt er. The receiver has an adaptive equali zer / DC restoration circuit for accura te clock / data r ecovery for the 100Ba se-TX signal. It also provides an on-ch ip low pass filer / Squelch circuit for the 10Base-T signal. MAC.
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