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S1L50000 Dataheets PDF



Part Number S1L50000
Manufacturers Epson
Logo Epson
Description HIGH DENSITY GATE ARRAY
Datasheet S1L50000 DatasheetS1L50000 Datasheet (PDF)

www.DataSheet4U.com DATA SHEET ASIC S1L50000 S1L50000 SERIES HIGH DENSITY GATE ARRAY Œ DESCRIPTION EPSON Electronics America, Inc.’s S1L50000 Series is a family of ultra high-speed VLSI CMOS gate array utilizing a 0.35µm “sea-of-gates” architecture. The S1L50000H products feature 5V tolerant I/O buffers. • • • Ultra-high-speed, high density and low power consumption Low voltage operation: 3.3V and 2.0V Number of raw gates: 28,710 ~ 815,468 gates Œ FEATURES • • • Process Integration Operat.

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www.DataSheet4U.com DATA SHEET ASIC S1L50000 S1L50000 SERIES HIGH DENSITY GATE ARRAY Œ DESCRIPTION EPSON Electronics America, Inc.’s S1L50000 Series is a family of ultra high-speed VLSI CMOS gate array utilizing a 0.35µm “sea-of-gates” architecture. The S1L50000H products feature 5V tolerant I/O buffers. • • • Ultra-high-speed, high density and low power consumption Low voltage operation: 3.3V and 2.0V Number of raw gates: 28,710 ~ 815,468 gates Œ FEATURES • • • Process Integration Operating Speed 0.35µm 2/3/4 layer metalization CMOS process A maximum of 815,468 gates (2 input NAND gate equivalent) Internal gates: 140 ps (3.3V Typ), 210 ps (2.0V Typ) (2-input pair NAND, F/O = 2, Typical wire load) Input buffer: 380 ps (5.0V Typ) Built-in level shifter is used. 400 ps (3.3V Typ), 1.30 ns (2.0V Typ) (F/O = 2, Typical wire load) Output buffer: 2.12 ns (5.0V Typ) Built-in level shifter is used. 2.02 ns (3.3 V Typ), 3.90 ns (2.0V Typ) (CL = 15 pF) Input/Output TTL/CMOS/LVTTL compatible TTL, CMOS, LVTTL, TTL Schmitt, CMOS Schmitt, LVTTL Schmitt, PCI Built-in pull-up and pull-down resistors can be usable. (2 types for each resistor value) Normal, 3-state, bi-directional, PCI IOL = 0.1, 1, 3, 8, 12, 24 mA selectable (Built-in level shifter is used at 5.0V) IOL = 0.1, 1, 2, 6, 12 mA selectable (at 3.3V) IOL = 0.05, 0.3, 0.6, 2, 4 mA selectable (at 2.0V) Asynchronous 1-port, asynchronous 2-port Operation supported by using level-shifter circuit Internal logic: Operation supported by low voltage I/O Buffer: Built-in interfaces of both high and low voltages possible • • I/F Levels Input Modes • • Output Modes Output Drive • • RAM Dual Power • Operation possible at VDD = 2.0 ± 0.2V EPSON ELECTRONICS AMERICA, INC. i150 River Oaks Pkwy iSan Jose, CA 95134 iTel: (408) 922-0200 iFax: (408) 922-0238 1 DATA SHEET ASIC S1L50000 Œ LINE UP The S1L50000 Series comprises 11 types of masters, from which the customer is able to select the master most suitable. Total BC (Raw Gates) 28710 75774 99198 125772 177062 250160 335858 442112 506688 668552 815468 Master S1L50282/283/284 S1L50752/753/754 S1L50992/993/994 S1L51252/253/254 S1L51772/773/774 S1L52502/503/504 S1L53352/353/354 S1L54422/423/424 S1L55062/063/064 S1L56682/683/684 S1L58152/153/154 Number of Pads 88 144 168 188 224 264 308 352 376 432 480 Number of Columns (X) 319 519 594 669 794 944 1094 1256 1344 1544 1706 Number of Rows (Y) 90 146 167 188 223 265 307 352 377 433 478 Cell Utilization Ratio (U)*1 2-layer 3-layer 4-layer metal metal metal 50% 47% 47% 45% 45% 45% 43% 40% 40% 40% 40% 88% 85% 85% 80% 75% 75% 75% 70% 70% 70% 70% 95% 95% 95% 95% 95% 95% 95% 90% 90% 90% 90% NOTE: *1: This is the value when there are no cells, such as RAM cells. The cell use efficiency is dependent not only on the scope of the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only as an estimate 2 EPSON ELECTRONICS AMERICA, INC. i 150 River Oaks Pkwy i San Jose, CA 95134 i Tel: (408) 922-0200 i Fax: (408) 922-0238 DATA SHEET ASIC S1L50000 Œ ELECTRICAL CHARACTERISTICS AND SPECIFICATIONS Absolute Maximum Ratings (For Single Power Supply): (Vss = 0V) Item Power Supply Voltage Input Voltage Output Voltage Output Current/Pin Storage Temperature * Symbol VDD VI VO IOUT TSTG Limits -0.3 to 4.0 *1 -0.3 to VDD + 0.5 *1 -0.3 to VDD + 0.5 ± 30 -65 to 150 V V V mA °C Unit 1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH systems. Absolute Maximum Ratings (For Dual Power Supplies): (Vss = 0V) Item Power Supply Voltage Symbol HVDD LVDD Limits -0.3 to 7.0 -0.3 to 4.0 -0.3 to HVDD + 0.5 -0.3 to LVDD + 0.5 *1 *1 *1 Unit V V V V V V mA °C Input Voltage HVI LVI Output Voltage HVO LVO -0.3 to HVDD + 0.5 -0.3 to LVDD + 0.5 ± 30 (± 50 ) -65 to 150 *2 *1 Output Current/Pin Storage Temperature ** IOUT TSTG 1: Possible to use from -0.3V to 7.5V of I/O buffer voltage in the open-drain systems and input buffer in the IDC and IDH systems. *2: Possible to use for 24mA of output buffer. EPSON ELECTRONICS AMERICA, INC. i150 River Oaks Pkwy iSan Jose, CA 95134 iTel: (408) 922-0200 iFax: (408) 922-0238 3 DATA SHEET ASIC S1L50000 Recommended Operating Conditions (For Single Power Supplies): Item Power Supply Voltage Input Voltage Ambient Temperature Normal Input for Rising Edge Input Normal Input for Falling Edge Input Schmitt Input for Rising Edge Input Schmitt Input for Falling Edge Input VDD VI Ta tri tfi tri tfi Symbol Min 3.00 VSS 0 -40 ----- Typ 3.30 -25 25 ----- Max 3.60 *1 VDD *2 70 *3 85 50 50 5 5 V V °C ns ns ms ms Unit *1: Possible to use 5.25 or 5.50V of I/O buffer in the open-drain systems and input buffer in the IDC and IDH systems. *2: The ambient temperature range is recommended for Tj = 0 to 80°C *3: The ambient temperature range is recommended for Tj = -40 to 125°C Recommended Operating Conditions (For Si.


RX-4045SA S1L50000 S3529B


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