Document
www.DataSheet4U.com
54AC138 • 54ACT138 1-of-8 Decoder/Demultiplexer
August 1998
54AC138 • 54ACT138 1-of-8 Decoder/Demultiplexer
General Description
The ’AC/’ACT138 is a high-speed 1-of-8 decoder/ demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three ’AC/’ACT138 devices or a 1-of-32 decoder using four ’AC/’ACT138 devices and one inverter.
Features
n n n n n n n ICC reduced by 50% Demultiplexing capability Multiple input enable for easy expansion Active LOW mutually exclusive outputs Outputs source/sink 24 mA ’ACT138 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’AC138: 5962-87622 — ’ACT138: 5962-87554
Logic Symbols
Connection Diagrams
Pin Assignment for DIP and Flatpak
DS100268-1
IEEE/IEC
DS100268-2
Pin Assignment for LCC
DS100268-7
Pin Names A0–A2 E1–E2 E3 O0–O7
Description Address Inputs Enable Inputs Enable Input Outputs
DS100268-3
FACT ® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100268
www.national.com
Functional Description
The ’AC/’ACT138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted inputs (A0, A1, A2) and, when enabled, provides eight mutually exclusive active-LOW outputs (O0–O7). The ’AC/’ACT138 features three Enable inputs, two active-LOW (E1, E2) and one active-HIGH (E3). All outputs will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four ’AC/’ACT138 devices and one inverter (see Figure 1). The ’AC/’ACT138 can be used as an 8-output demultiplexer by using one of the active LOW Enable inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used must be permanently tied to their appropriate active-HIGH or active-LOW state.
Truth Table
Inputs E1 H X X L L L L L L L L E2 X H X L L L L L L L L E3 X X L H H H H H H H H A0 X X X L H L H L H L H A1 X X X L L H H L L H H A2 X X X L L L L H H H H O0 H H H L H H H H H H H O1 H H H H L H H H H H H O2 H H H H H L H H H H H Outputs O3 H H H H H H L H H H H O4 H H H H H H H L H H H O5 H H H H H H H H L H H O6 H H H H H H H H H L H O7 H H H H H H H H H H L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
www.national.com
2
Logic Diagram
DS100268-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.national.com
www.national.com
Logic Diagram
(Continued)
4
DS100268-5
FIGURE 1. Expansion to 1-of-32 Decoding
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI =.