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ICS853058 Dataheets PDF



Part Number ICS853058
Manufacturers ICST
Logo ICST
Description LVPECL/ECL CLOCK MULTIPLEXER
Datasheet ICS853058 DatasheetICS853058 Datasheet (PDF)

www.DataSheet4U.com PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER FEATURES • High speed 8:1 differential multiplexer • 1 differential 3.3V or 2.5V LVPECL output • 8 selectable differential PCLK, nPCLK inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: 2.5GHz • Translates any single ended input signal to LVPECL levels with resistor bias on nPC.

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www.DataSheet4U.com PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER FEATURES • High speed 8:1 differential multiplexer • 1 differential 3.3V or 2.5V LVPECL output • 8 selectable differential PCLK, nPCLK inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: 2.5GHz • Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input • Part-to-part skew: TBD • Propagation delay: 620ps (typical) • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to -2.375V • -40°C to 85°C ambient operating temperature GENERAL DESCRIPTION The ICS853058 is an 8:1 Differential-to-3.3V or 2.5V LVPECL / ECL Clock Multiplexer which can HiPerClockS™ operate up to 2.5GHz and is a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS853058 has 8 differential selectable clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. The SEL2 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 000 selects PCLK0, nPCLK0). ICS BLOCK DIAGRAM PCLK0 nPCLK0 PCLK1 nPCLK1 PCLK2 nPCLK2 PCLK3 nPCLK3 PCLK4 nPCLK4 PCLK5 nPCLK5 PCLK6 nPCLK6 PCLK7 nPCLK7 PIN ASSIGNMENT PCLK0 nPCLK0 PCLK1 nPCLK1 VCC SEL0 SEL1 SEL2 PCLK2 nPCLK2 PCLK3 nPCLK3 Q0 nQ0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 000 001 010 011 PCLK7 nPCLK7 PLCK6 nPCLK6 VCC Q0 nQ0 VEE PCLK5 nPCLK5 PCLK4 nPCLK4 100 ICS853058 24-Lead, 173-MIL TSSOP 4.4mm x 7.8mm x 0.92mm body package G Package Top View 101 110 111 SEL2 SEL1 SEL0 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 853058AG www.icst.com/products/hiperclocks.html REV. A APRIL 13, 2004 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER Type Input Input Input Input Power Input Input Input Input Input Input Input Input Input Power Output Input Input Input Input Pullup/Pulldown Pulldown Pullup/Pulldown Pulldown Pulldown Pulldown Pulldown Description Non-inver ting differential LVPECL clock input. TABLE 1. PIN DESCRIPTIONS Number 1 2 3 4 5, 20 6, 7, 8 9 10 11 12 13 14 15 16 17 18, 19 21 22 23 24 Name PCLK0 nPCLK0 PCLK1 nPCLK1 VCC SEL0, SEL1, SEL2 PCLK2 nPCLK2 PCLK3 nPCLK3 nPCLK4 PCLK4 nPCLK5 PCLK5 VEE nQ0, Q0 nPCLK6 PCLK6 nPCLK7 PCLK7 Inver ting differential LVPECL clock input. Pullup/Pulldown VCC/2 default when left floating. Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pullup/Pulldown VCC/2 default when left floating. Positive supply pins. Clock select input pins. LVCMOS/LVTTL interface levels. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pullup/Pulldown VCC/2 default when left floating. Pulldown Pullup/Pulldown Pullup/Pulldown Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pullup/Pulldown VCC/2 default when left floating. Pulldown Non-inver ting differential LVPECL clock input. Negative supply pin. Differential output pair. LVPECL interface levels. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 853058AG www.icst.com/products/hiperclocks.html 2 REV. A APRIL 13, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS853058 8:1, DIFFERENTIAL-TO3.3V OR 2.5V LVPECL/ECL CLOCK MULTIPLEXER Test Conditions Minimum Typical 75 50 Maximum Units KΩ KΩ TABLE 2. PIN CHARACTERISTICS Symbol RPULLDOWN RVDD/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistosr TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 Q0 PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6 PCLK7 Outputs nQ0 nPCLK0 nPCLK1 nPCLK2 nPCLK3 nPCLK4 nPCLK5 nPCLK6 nPCLK7 853058AG www.icst.com/products/hiperclocks.html 3 REV. A APRIL 13, 2004 PREL.


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