ICS8530I-01

www.DataSheet4U.com PRELIMINARY Integrated Circuit Systems, Inc. ICS8530I-01 LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER FEATURES (16) differential 3.3V LVPECL outputs CLK, nCLK input pair CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL Maximum output frequency: 500MHz Translates any single-ended input signal to 3.3V LVPECL levels with a resistor bias on nCLK input Output skew: 50ps (typical) Part-to-part skew: 100ps (typical) Additive phase jitter, RMS @ 106.25MHz: 0.022ps (typical) @ 25°C 3.3V output operating supply -40°C to 85°C ambient operating temperature GENERAL DESCRIPTION The ICS8530I-01 is a low skew, 1-to-16 Differential-to-3.3V LVPECL Fanout Buffer and a memHiPerClockS™ ber of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The high gain differential amplifier accepts peak-topeak input voltages as small as 150mV as long as the common mode voltage is within the specified minimum and maximum range. ICS Guaranteed output and part-to-part skew characteristics make the ICS8530I-01 ideal for those clock distribution applications demanding well defined performance and repeatability. BLOCK DIAGRAM CLK nCLK PIN ASSIGNMENT nCLK VCCO Q15 nQ15 Q14 nQ14 VEE Q13 nQ13 Q12 nQ12 VCCO 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 1...