Document
www.DataSheet4U.com
Integrated Circuit Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
FEATURES
• 9 differential 3.3V LVPECL outputs • Selectable CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency up to 500MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 50ps (maximum) • Part-to-part skew: 250ps (maximum) • Propagation delay: 2ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8531-01 is a low skew, high performance 1-to-9 Differential-to-3.3V LVPECL Fanout Buffer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8531-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
,&6
Guaranteed output skew and part-to-part skew characteristics make the ICS8531-01 ideal for high performance workstation and server applications.
BLOCK DIAGRAM
CLK_EN CLK nCLK PCLK nPCLK CLK_SEL D Q LE 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7 Q8 nQ8
PIN ASSIGNMENT
VCCO VCCO nQ0 nQ1 nQ2 Q0 Q1 Q2
32 31 30 29 28 27 26 25 VCC CLK nCLK CLK_SEL PCLK nPCLK VEE CLK_EN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Vcco nQ8 Q8 nQ7 Q7 nQ6 Q6 Vcco
24 23 22 21 20 19 18 17
VCCO Q3 nQ3 Q4 nQ4 Q5 nQ5 VCCO
ICS8531-01
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View
8531AY-01
www.icst.com/products/hiperclocks.html
1
REV. B AUGUST 9, 2001
Integrated Circuit Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
Type Power Input Input Input Input Input Power Input Power Output Output Output Output Output Output Output Output Output Pullup Pulldown Pullup Pulldown Pulldown Pullup Description Positive supply pin. Connect to 3.3V. Non-inver ting differential clock input. Inver ting differential clock input. Clock Select input. When HIGH, selects PCLK, nPCLK inputs. When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Negative supply pin. Connect to ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. Output supply pins. Connect to 3.3V. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interface level. Differential output pair. LVPECL interfa.