CY7C1353

www.DataSheet4U.com 1353 CY7C1353 256Kx18 Flow-Through SRAM with NoBL™ Architecture Features Pin compatible and functionally equivalent to ZBT™ devices MCM63Z819 and MT55L256L18F Supports 66-MHz bus operations with zero wait states — Data is transferred on every clock Internally self-timed output buffer control to eliminate the need to use OE Registered inputs for Flow-Through operation Byte Write capability 256K x 18 common I/O architecture Single 3.3V power supply Fast clock-to-output times — 11.0 ns (for 66-MHz device) — 12. 0 ns (for 50-MHz device) — 14.0 ns (for 40-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes Asynchronous Output Enable JEDEC-standard 100 TQFP package Burst Capability—linear or interleaved burst order Low standby power Functional Description The CY7C1353 is a 3.3V 256K by 18 SynchronousFlow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353 is equipped with the advanced No Bus Latency (NoBL ™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.The CY7C1353 is pin/functionally compatible to ZBT™ SRAMs MCM63Z819 and MT55L256L18F. All synchronous inputs pass through input registers control...