MC10110

www.DataSheet4U.com MC10110 Dual 3-Input/3-Ouput OR Gate The ability to control three parallel lines from a single point makes the MC10110 particularly useful in clock distribution applications where minimum clock skew is desired. Three VCC pins are provided and each one should be used. PD = 80 mW typ/pkg (No Load) tpd = 2.4 ns typ (All Outputs Loaded) tr, tf = 2.2 ns typ (20%–80%) LOGIC DIAGRAM 5 6 7 2 3 4 12 13 14 http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 1 16 PDIP–16 P SUFFIX CASE 648 1 1 MC10110P AWLYYWW MC10110L AWLYYWW 9 10 11 VCC1 = PIN 1, 15 VCC2 = PIN 16 VEE = PIN 8 PLCC–20 FN SUFFIX CASE 775 10101 AWLYYWW DIP PIN ASSIGNMENT A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week VCC1 AOUT AOUT AOUT AIN AIN AIN VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 VCC1 BOUT BOUT BOUT BIN BIN BIN MC10110P ORDERING INFORMATION Device MC10110L Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail MC10110FN Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). © Semiconductor Components Industries, LLC, 2000 1 March, 2000 – Rev. 7 Publication Order Number: MC10110/D MC10110 ELECTRICAL CHARACTERISTICS Test Limits Pin Under Test 8 5, 6, 7 5, 6, 7 2 3 4 2 3 4 2 3 4 2 3 4 0.5 –1.060 –1.060 –1.060 –1.890 –1.890 –1.890 –1.080 –1.080 –1.080 –1.655 –1.655 –1.655 –0.890 –0.890 –0.890 –1.675 –1.6...