LFEC40

www.DataSheet4U.com LatticeECP/EC Family Data Sheet Version 01.3 LatticeECP/EC Family Data Sheet Introduction November 2004 Preliminary Data Sheet Features ■ Extensive Density and Package Options 1.5K to 41K LUT4s 65 to 576 I/Os Density migration supported − − − − − − LVCMOS 3.3/2.5/1.8/1.5/1.2 LVTTL SSTL 3/2 Class I, II, SSTL18 Class I HSTL 18 Class I, II, III, HSTL15 Class I, III PCI LVDS, Bus-LVDS, LVPECL, RSDS ■ sysDSP™ Block (LatticeECP™ Versions) High performance multiply and accumulate 4 to 10 blocks − 4 to 10 36x36 multipliers or – 16 to 40 18x18 multipliers or − 32 to 80 9x9 multipliers ■ Dedicated DDR Memory Support Implements interface up to DDR400 (200MHz) ■ sysCLOCK™ PLLs Up to 4 analog PLLs per device Clock multiply, divide and phase shifting ■ Embedded and Distributed Memory 18 Kbits to 645 Kbits sysMEM™ Embedded Block RAM (EBR) Up to 163 Kbits distributed RAM Flexible memory resources: − Distributed and block memory ■ System Level Support IEEE Standard 1149.1 Boundary Scan, plus ispTRACY™ internal logic analyzer capability SPI boot flash interface 1.2V power supply ■ Low Cost FPGA Features optimized for mainstream applications Low cost TQFP and PQFP packaging ■ Flexible I/O Buffer Programmable sysIO™ buffer supports wide range of interfaces: Table 1-1. LatticeECP/EC Family Selection Guide Device PFU/PFF Rows PFU/PFF Columns PFUs/PFFs LUTs (K) Distributed RAM (Kbits) EBR SRAM (Kbits) EBR SRAM Blocks sysDSP Blocks 1 ...