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74LVC132A Dataheets PDF



Part Number 74LVC132A
Manufacturers NXP
Logo NXP
Description Quad 2-Input NAND Schmitt Trigger
Datasheet 74LVC132A Datasheet74LVC132A Datasheet (PDF)

www.DataSheet4U.com 74LVC132A Quad 2-input NAND Schmitt trigger Rev. 01 — 15 December 2006 Product data sheet 1. General description The 74LVC132A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for .

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www.DataSheet4U.com 74LVC132A Quad 2-input NAND Schmitt trigger Rev. 01 — 15 December 2006 Product data sheet 1. General description The 74LVC132A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT− is defined as the input hysteresis voltage VH. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environment. 2. Features s s s s s s s s Wide supply voltage range from 2.3 V to 3.6 V 5 V tolerant inputs for interfacing with 5 V logic CMOS low power consumption Direct interface with TTL levels Unlimited rise and fall times Inputs accept voltages up to 5.5 V Complies with JEDEC standard JESD8-B/JESD36 ESD protection: x HBM JESD22-A114-D exceeds 2000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Applications s Wave and pulse shaper s Astable multivibrator s Monostable multivibrator. www.DataSheet4U.com NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 4. Ordering information Table 1. Ordering information Package Temperature range Name 74LVC132AD −40 °C to +125 °C SO14 TSSOP14 Description plastic small outline package; 14 leads; body width 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT108-1 SOT402-1 SOT762-1 Type number 74LVC132APW −40 °C to +125 °C 74LVC132ABQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 5. Functional diagram 1 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 2 4 2Y 6 5 9 10 12 13 mna212 & 3 & 6 3Y 8 & 8 A 4Y 11 & mna246 11 B Y 001aac532 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 2 of 15 www.DataSheet4U.com NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 6. Pinning information 6.1 Pinning 74LVC132A terminal 1 index area 14 VCC 13 4B 12 4A 11 4Y GND(1) 7 8 10 3B 9 GND 3Y 3A 1A 2 3 4 5 6 1 1B 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 001aaf590 74LVC132A 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 8 3A 3Y 2Y 1Y 2A 2B 001aaf591 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 6.2 Pin description Table 2. Symbol 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description data input data input data output data input data input data output ground (0 V) data output data input data input data output data input data input supply voltage 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 3 of 15 www.DataSheet4U.com NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 7. Functional description Table 3. Input nA L L H H [1] H = HIGH voltage level; L = LOW voltage level. Function table[1] Output nB L H L H nY H H H L 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input voltage output voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation Conditions [1] [1] Min −0.5 −0.5 −0.5 −50 −100 −65 Max +6.5 +6.5 VCC + 0.5 ±50 ±50 100 +150 500 Unit V V V mA mA mA mA mA °C mW VI < 0 V VO > VCC or VO < 0 V VO = 0 V to VCC Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SO14 packages: Ptot derates linearly with 8 mW/K above 70 °C. For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C. 9. Recommended operating conditions Table 5. Symbol VCC VI VO Tamb Recommended operating conditions Parameter supply voltage input voltage output voltage ambient temperature Conditions Min 1.2 0 0 −40 Typ Max 3.6 5.5 VCC +125 Unit V V V °C 74LVC132A_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 15 December 2006 4 of 15 w w w . D a t a S h e e t 4 U . c o m NXP Semiconductors 74LVC132A Quad 2-input NAND Schmitt trigger 10. Static characteristics Table 6. S.


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