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KS8995XA
Micrel, Inc.
KS8995XA
Integrated 5-Port 10/100 QoS Switch Rev. 2.3
General Description
The KS8995XA is a highly integrated Layer-2 quality of service (QoS) switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set including three different QoS priority schemes, a dual MII interface for BOM cost reduction, rate limiting to offload CPU tasks, software and hardware power-down, a MDC/MDIO control interface and port mirroring/monitoring to effectively address both current and emerging Fast Ethernet applications. The KS8995XA contains five 10/100 transceivers with patented mixed-signal low-power technology, five media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. All PHY units support 10BASE-T and 100BASE-TX. In addition, two of the PHY units support 100BaseFX (Ports 4 and 5).
Features
• Integrated switch with five MACs and five Fast Ethernet transceivers fully compliant to IEEE 802.3u standard • Shared memory based switch fabric with fully nonblocking configuration • 10BASE-T, 100BASE-TX and 100BASE-FX modes (FX in Ports 4 and 5) • Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII) • VLAN ID tag/untag options, per-port basis • Enable/disable option for huge frame size up to 1916 bytes per frame • Broadcast storm protection with percent control – global and per-port basis • Optimization for fiber-to-copper media conversion • Full-chip hardware power-down support (register configuration not saved) • Per-port-based software power-save on PHY (idle link detection, register configuration preserved) • QoS/CoS packets prioritization supports: per port, 802.1p and DiffServ-based
Functional Diagram
Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X Auto MDI/MDI-X MII-P5 MDC, MDI/O MII-SW or SNI LED0[5:1] LED1[5:1] LED2[5:1]
10/100 T/Tx 1 10/100 T/Tx 2 10/100 T/Tx 3 10/100 T/Tx/Fx 4 10/100 T/Tx/Fx 5
10/100 MAC 1
1K Look-Up Engine
FIFO, Flow Control, VLAN Tagging, Priority
10/100 MAC 2 10/100 MAC 3 10/100 MAC 4 10/100 MAC 5 SNI
Queue Mgmnt
Buffer Mgmnt
Frame Buffers
LED I/F
Control Registers
EEPROM I/F
KS8995XA
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
May 2005
1
M9999-051305
KS8995XA
Micrel, Inc.
Features (continued)
• 802.1p/q tag insertion or removal on a per-port basis (egress) • Port-based VLAN support • MDC and MDI/O interface support to access the MII PHY control registers (not all control registers) • MII local loopback support • On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table) • 1.4Gbps high performance memory bandwidth • Wire-speed reception and transmission • Integrated look-up engine with dedicated 1K unicast MAC addresses • Automatic address learning, address aging and address migration • Full-duplex IEEE 802.3x and half-duplex back pressure flow control • Comprehensive LED support • 7-wire SNI support for legacy MAC interface • Automatic MDI/MDI-X crossover for plug-and-play • Disable automatic MDI/MDI-X option • Low power Core: 1.8V I/O: 2.5 or 3.3V • 0.18µm CMOS technology • Commercial temperature range: 0°C to +70°C • Available in 128-pin PQFP package
Applications
• • • • • • • • • Broadband gateway/firewall/VPN Integrated DSL or cable modem multi-port router Wireless LAN access point plus gateway Home networking expansion Standalone 10/100 switch Hotel/campus/MxU gateway Enterprise VoIP gateway/phone FTTx customer premise equipment Media converter
Ordering Information
Part Number KS8995XA KSZ8995XA Temp. Range 0°C to +70°C 0°C to +70°C Package 128-Pin PQFP 128-Pin PQFP Lead Finish Standard Pb-Free
M9999-051305
2
May 2005
KS8995XA
Micrel, Inc.
Revision History
Revision 2.0 2.1 2.2 2.3 Date 10/15/03 4/1/04 1/19/05 4/13/05 Summary of Changes Created. Editorial changes on TTL input and output electrical characteristics. Insert recommeneded reset circuit. Switched pins names for pins 7 & 8 on page 16. Changed VDDIO to 3.3V. Changed Jitter to 16 ns Max.
May 2005
3
M9999-051305
KS8995XA
Micrel, Inc.
Table of Contents
System Level Applications .............................................................................................................................................................. 6 Pin Description (by Number) ........................................................................................................................................................... 8 Pin Description (by Name) ............................................................................................................................................................ 13 Pin Configuration ..............................................................................................................