HY5PS12821F

www.DataSheet4U.com HY5PS12421(L)F HY5PS12821(L)F HY5PS121621(L)F 512Mb DDR2 SDRAM HY5PS12421(L)F HY5PS12821(L)F HY5PS121621(L)F This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0/ Feb. 2005 1 1HY5PS12421(L)F HY5PS12821(L)F HY5PS121621(L)F Revision History Rev. 0.0 0.1 0.2 Preliminary Changed Some Description & IDD Spec Editorial clean up, Fixed CL3~6 & AL0~5, Defined IDD Specifications, Added Package outline, added Self-Refresh High temperature Entry, changed tRAS spec. for DDR2 400 Transfered Functional description, command truth table pages and Some contents of Operating conditions to Modified IDD specifications. Changed IDD Spec.(IDD2P & IDD6) History Draft Date Apr.2003 Jun. 2003 Dec. 2003 Jul. 2004 Nov. 2004 Feb. 2005 1.0 Rev. 1.0 / Feb. 2005 2 1HY5PS12421(L)F HY5PS12821(L)F HY5PS121621(L)F Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Feaures 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.3 Pin Description 2. Maximum DC ratings 2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition 3. AC & DC Operating Conditions 3.1 DC Operating Conditions 5.1.1 Recommended DC Operating Conditions(SSTL_1.8) 5.1.2 ODT DC Electrical Characteristics 3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level 3.2.2 Input AC ...