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HY5PS1G831F Dataheets PDF



Part Number HY5PS1G831F
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description (HY5PS1G431F / HY5PS1G831F) 1Gb DDR2 SDRAM
Datasheet HY5PS1G831F DatasheetHY5PS1G831F Datasheet (PDF)

www.DataSheet4U.com HY5PS1G431(L)F HY5PS1G831(L)F 1Gb DDR2 SDRAM HY5PS1G431(L)F HY5PS1G831(L)F This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.2 / Apr. 2004 1 www.DataSheet4U.com HY5PS1G431(L)F HY5PS1G831(L)F Revision Details Revision No. 0.1 0.2 History Preliminary Corrected typos of Pin description & tRFC spec. , Added IDD spec. .

  HY5PS1G831F   HY5PS1G831F



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www.DataSheet4U.com HY5PS1G431(L)F HY5PS1G831(L)F 1Gb DDR2 SDRAM HY5PS1G431(L)F HY5PS1G831(L)F This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.2 / Apr. 2004 1 www.DataSheet4U.com HY5PS1G431(L)F HY5PS1G831(L)F Revision Details Revision No. 0.1 0.2 History Preliminary Corrected typos of Pin description & tRFC spec. , Added IDD spec. Draft Date Feb.2004 Apr.2004 Remark Initial Release Rev 0.2 / Apr. 2004 2 www.DataSheet4U.com HY5PS12421(L)F HY5PS12821(L)F HY5PS121621(L)F Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Feaures 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.2.1 256M × 4 DDR2 Pin Configuration 1.2.2 128M × 8 DDR2 Pin Configuration 1.3 Pin Description 2. Functioanal Description 2.1 Simplified State Diagram 2.2 Functional Block Diagram 2.2.1 Functional Block Diagram(256M × 4) 2.2.2 Functional Block Diagram(128M × 8) 2.3 Basic Function & Operation of DDR2 SDRAM 2.3.1 Power up and Initialization 2.3.2 Programming the Mode and Extended Mode Registers 2.3.2.1 DDR2 SDRAM Mode Register Set(MRS) 2.3.2.2 DDR2 SDRAM Extended Mode Register Set 2.3.2.3 Off-Chip Driver(OCD) Impedance Adjustment 2.3.2.4 ODT(On Die Termination) 2.4 Bank Activate Command 2.5 Read and Write Command 2.5.1 Posted CAS 2.5.2 Burst Mode Operation 2.5.3 Burst Read Command 2.5.4 Burst Write Operation 2.5.5 Write Data Mask 2.6 Precharge Operation 2.7 Auto Precharge Operation 2.8 Refresh Commands 2.8.1 Auto Refresh Command 2.8.2 Self Refresh Command 2.9 Power Down 2.10 Asynchronous CKE Low Event 2.11 No Operation Command 2.12 Deselect Command 3. Truth Tables 3.1 Command Truth Table 3.2 Clock Enable(CKE) Truth Table for Synchronous Transistors 3.3 Data Mask Truth Table 4. Operating Conditions 4.1 Absolute Maximum DC Ratings 4.2 Operating Temperature Condition Rev 0.1 / Feb. 2004 3 www.DataSheet4U.com HY5PS12421(L)F HY5PS12821(L)F HY5PS121621(L)F 5. AC & DC Operating Conditions 5.1 DC Operation Conditions 5.1.1 Recommended DC Operating Conditions(SSTL_1.8) 5.1.2 ODT DC Electrical Characteristics 5.2 DC & AC Logic Input Levels 5.2.1 Input DC Logic Level 5.2.2 Input AC Logic Level 5.2.3 AC Input Test Conditions 5.2.4 Differential Input AC Logic Level 5.2.5 Differential AC output parameters 5.2.6 Overshoot / Undershoot Specification 5.3 Output Buffer Levels 5.3.1 Output AC Test Conditions 5.3.2 Output DC Current Drive 5.3.3 OCD default chracteristics 5.4 Default Output V-I Characteristics 5.4.1 Full Strength Default Pulldown Driver Characteristics 5.4.2 Full Strength Default Pullup Driver Chracteristics 5.4.3 Calibrated Output Driver V-I Characteristics 5.5 Input/Output Capacitance 6. IDD Specifications & Measurement Conditions 7. AC Timing Specifications 7.1 Timing Parameters by Speed Grade 7.2 General Notes for all AC Parameters 7.3 Specific Notes.


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