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256Mb DDR SDRAM
HY5DU56822E(L)TP HY5DU561622E(L)TP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 /June. 2006 1
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HY5DU56822E(L)TP HY5DU561622E(L)TP
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Revision History
Revision No. 1.0 1.1 First release Added CL2 & CL2.5 values to the DDR400B in the AC CHARACTERISTICS History Draft Date Apr. 2006 June 2006 Remark
Rev. 1.1 /June. 2006
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HY5DU56822E(L)TP HY5DU561622E(L)TP
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DESCRIPTION
The HY5DU56822E(L)TP and HY5DU561622E(L)TP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
FEATURES
• • • • • • • VDD, VDDQ = 2.5V +/- 0.2V for DDR200, 266, 333 VDD, VDDQ = 2.6V +0.1V / -0.2V for DDR400 All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe • • • • • • • • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 2/2.5 (DDR200, 266, 333) and 3 (DDR400) supported Programmable burst length 2/4/8 with both sequential and interleave mode Internal four bank operations with single pulsed /RAS Auto refresh and self refresh supported tRAS lock out function supported 8192 refresh cycles/64ms JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Lead free (*ROHS Compliant)
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ORDERING INFORMATION
Part No. HY5DU56822E(L)TP-X* HY5DU561622E(L)TP-X* Configuration 32Mx8 16Mx16 Package 400mil 66pin TSOP-II**
OPERATING FREQUENCY
Grade -D43 -J -K -H -L Clock Rate 200MHz@CL3 133MHz@CL2 133MHz@CL2 100MHz@CL2
[email protected] [email protected] [email protected] Remark (CL-tRCD-tRP) DDR400B (3-3-3) DDR333 (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3) DDR200 (2-2-2)
* X means speed grade ** Lead-free product *ROHS (Restriction Of Hazardous Substances)
100MHz@CL2
Rev. 1.1 /June. 2006
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