IDT71V65702

www.DataSheet4U.com 256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs x x x x x x x x x x x x IDT71V65702 IDT71V65902 Features 256K x 36, 512K x 18 memory configurations Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin 4-word burst capability (Interleaved or linear) Individual byte write (BW1-BW4) control (May tie active) Three chip enables for simple depth expansion 3.3V power supply (±5%) 2.5V (±5%) I/O Supply (VDDQ) Power down controlled by ZZ input Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA). Description The IDT71V65702/5902 are 3.3V high-speed 9,437,184-bit (9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and on the next clock cycle the associated data cycle occurs, be it read or write. The IDT71V65702/5902 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). Output enable is the only asynchro...