STATIC RAM. IDT709189L Datasheet

IDT709189L RAM. Datasheet pdf. Equivalent

Part IDT709189L
Description HIGH-SPEED 64K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Feature www.DataSheet4U.com HIGH-SPEED 64K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features x x IDT.
Manufacture IDT
Datasheet
Download IDT709189L Datasheet



IDT709189L
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HIGH-SPEED 64K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709189L
Features
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
x Low-power operation
– IDT709189L
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
x Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
x Counter enable and reset features
x Dual chip enables allow for depth expansion without
additional logic
x Full synchronous operation on both ports
4ns setup to clock and 0ns hold on all control, data, and
address inputs
Data input, address, and control registers
Fast 7.5ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
12ns cycle time, 83MHz operation in Pipelined output mode
x TTL- compatible, single 5V (±10%) power supply
x Industrial temperature range (–40°C to +85°C) is
available for selected speeds
x Available in a 100-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
A15L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
FT/PIPER
I/O0R - I/O8R
A15R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4848 drw 01
©2000 Integrated Device Technology, Inc.
1
JANUARY 2001
DSC-4848/3



IDT709189L
IDT709189L
High-Speed 64K x 9 Synchronous Pipelined Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT709189 is a high-speed 64K x 9 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
With an input data register, the IDT709189 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by CE0 and CE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 1.2W of power.
Pin Configurations(1,2,3)
Index
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
A15L
NC
VCC
NC
NC
NC
NC
CE0L
CE1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
1 100 99 98
97 96 95
94 93
92
91 90
89
88
87 86
85 84
83 82 81
80 79
78 77
76
75
2 74
3 73
4 72
5 71
6 70
7 69
8 68
9 67
10 IDT709189PF 66
11 PN100-1(4) 65
12 64
13 100-Pin TQFP 63
14 Top View(5) 62
15 61
16 60
17 59
18 58
19 57
20 56
21 55
22 54
23 53
24 52
25 51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
NC
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
,
4848 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.242





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