AND8048D G-S MOSFET Datasheet

AND8048D Datasheet, PDF, Equivalent


Part Number

AND8048D

Description

Dual P-Channel 1.8 V (G-S) MOSFET

Manufacture

ON Semiconductor

Total Page 8 Pages
Datasheet
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AND8048D
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AND8048/D
SPICE Device Model
NTHD5905T1
Dual P–Channel 1.8 V (G–S) MOSFET
http://onsemi.com
APPLICATION NOTE
CHARACTERISTICS
P–Channel Vertical DMOS
Macro–Model (Sub–circuit)
Level 3 MOS
Applicable for both Linear and Switch Mode
Applicable over a –55 to 125°C Temperature Range
Models Gate Charge, Transient, and Diode Reverse
Recovery Characteristics
DESCRIPTION
The attached SPICE Model describes typical electrical
characteristics of the p–channel vertical DMOS. The
sub–circuit model was extracted and optimized over a 25°C
to 125°C temperature range under pulse conditions for 0 to
–5 volts gate drives. Saturated output impedance model
accuracy has been maximized for gate biases near
threshold. A novel gate–to–drain feedback capacitor
network is used to model gate charge characteristics while
avoiding convergence problems of switched Cgd model.
Model parameter values are optimized to provide a best fit
to measure electrical data and are not intended as an exact
physical description of a device.
D
4
M
R
M3
DB
G
1
CGS
2
S
Figure 1. Model Sub–circuit
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
© Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 0
1
Publication Order Number:
AND8048/D

AND8048D
AND8048/D
MODEL EVALUATION
P–CHANNEL DEVICE (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Static
Gate Threshold Voltage
On–State Drain Current (Note 1.)
Drain–Source On–State Resistance (Note 1.)
VGS(th)
ID(on)
rDS(on)
Forward Transconductance (Note 1.)
Diode Forward Voltage (Note 1.)
Dynamic (Note 2.)
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Source–Drain Reverse Recovery Time
1. Pulse test: pulse width  300 ms, duty cycle  2%.
2. Guaranteed by design, not subject to production testing.
gfs
VSD
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
trr
Test Conditions
VDS = VGS, ID = –250 mA
VDS  –5.0 V, VGS = 4.5 V
VGS = –4.5 V, ID = –3.0 A
VGS = –2.5 V, ID = –2.5 A
VGS = –1.8 V, ID = –1.0 A
VDS = 5.0 V, ID = 3.0 A
IS = –0.9 A, VGS = 0.0 V
VDS = –4.0 V, VGS = –4.5 V, ID = –3.0 A
VDD = –4.0 V, RL = 4.0 W, ID ^ –1.0 A,
VGEN = –4.5 V, RG = 6.0 W
IF = –0.9 A, di/dt = 100 A/ms
Typical Unit
0.83
36
0.080
0.110
0.142
7.6
–0.80
V
A
W
S
V
35
0.5 nC
1.5
13
19
24 ns
12
28
http://onsemi.com
2


Features www.DataSheet4U.com AND8048/D SPICE Dev ice Model NTHD5905T1 Dual P–Channel 1 .8 V (G–S) MOSFET http://onsemi.com APPLICATION NOTE CHARACTERISTICS DESCRI PTION • • • • • • P–Cha nnel Vertical DMOS Macro–Model (Sub circuit) Level 3 MOS Applicable for bo th Linear and Switch Mode Applicable ov er a –55 to 125°C Temperature Range Models Gate Charge, Transient, and Diod e Reverse Recovery Characteristics The attached SPICE Model describes typical electrical characteristics of the p– channel vertical DMOS. The sub–circui t model was extracted and optimized ove r a 25°C to 125°C temperature range u nder pulse conditions for 0 to –5 vol ts gate drives. Saturated output impeda nce model accuracy has been maximized f or gate biases near threshold. A novel gate–to–drain feedback capacitor ne twork is used to model gate charge char acteristics while avoiding convergence problems of switched Cgd model. Model p arameter values are optimized to provide a best fit to measure electrical data and are not intended .
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