HY57V56820BLT Synchronous DRAM Datasheet

HY57V56820BLT Datasheet, PDF, Equivalent


Part Number

HY57V56820BLT

Description

4 Banks x 8M x 8Bit Synchronous DRAM

Manufacture

Hynix Semiconductor

Total Page 12 Pages
Datasheet
Download HY57V56820BLT Datasheet


HY57V56820BLT
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HY57V56820B(L)T
4 Banks x 8M x 8Bit Synchronous DRAM
DESCRIPTION
The HY57V56820B is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large
memory density and high bandwidth. The HY57V56820B is organized as 4banks of 8,388,608x8.
The HY57V56820B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or
write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
• All inputs and outputs referenced to positive edge of system
clock
• Data mask function by DQM
• Auto refresh and self refresh
• 8192 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
• Internal four banks operation
ORDERING INFORMATION
Part No.
HY57V56820BT-6
HY57V56820BT-K
HY57V56820BT-H
HY57V56820BT-8
HY57V56820BT-P
HY57V56820BT-S
HY57V56820BLT-6
HY57V56820BLT-K
HY57V56820BLT-H
HY57V56820BLT-8
HY57V56820BLT-P
HY57V56820BLT-S
Clock Frequency
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Power
Normal
Low power
Organization
4Banks x 8Mbits x8
Interface
Package
LVTTL
400mil 54pin TSOP II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 1.4/Mar. 02
1

HY57V56820BLT
PIN CONFIGURATION
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
VDD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
HY57V56820B(L)T
PIN DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A12
RAS, CAS, WE
DQM
DQ0 ~ DQ7
VDD/VSS
VDDQ/VSSQ
NC
PIN NAME
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA9
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 1.4/Mar. 02
2


Features www.DataSheet4U.com HY57V56820B(L)T 4 B anks x 8M x 8Bit Synchronous DRAM DESCR IPTION The HY57V56820B is a 268,435,456 bit CMOS Synchronous DRAM, ideally suit ed for the main memory applications whi ch require large memory density and hig h bandwidth. The HY57V56820B is organiz ed as 4banks of 8,388,608x8. The HY57V5 6820B is offering fully synchronous ope ration referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of th e clock input. The data paths are inter nally pipelined to achieve very high ba ndwidth. All input and output voltage l evels are compatible with LVTTL. Progra mmable options include the length of pi peline (Read latency of 2 or 3), the nu mber of consecutive read or write cycle s initiated by a single control command (Burst length of 1,2,4,8 or full page) , and the burst count sequence(sequenti al or interleave). A burst of read or w rite cycles in progress can be terminat ed by a burst terminate command or can be interrupted and repla.
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