CY7C1351 Flow-Through SRAM Datasheet

CY7C1351 Datasheet, PDF, Equivalent


Part Number

CY7C1351

Description

128Kx36 Flow-Through SRAM

Manufacture

Cypress Semiconductor

Total Page 13 Pages
Datasheet
Download CY7C1351 Datasheet


CY7C1351
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CY7C1351
128Kx36 Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
Pin compatible and functionally equivalent to ZBT™ de-
vices IDT71V547, MT55L128L36F, and MCM63Z737
• Supports 66-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for Flow-Through operation
• Byte Write capability
• 128K x 36 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 11.0 ns (for 66-MHz device)
— 12.0 ns (for 50-MHz device)
— 14.0 ns (for 40-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
Low standby power
The CY7C1351 is a 3.3V, 128K by 36 Synchronous
Flow-Through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1351 is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to en-
able consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data through the SRAM, especially in sys-
tems that require frequent Write/Read transitions. The
CY7C1351 is pin/functionally compatible to ZBT SRAMs
IDT71V547, MT55L128L36F, and MCM63Z737.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock.The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted sus-
pends operation and extends the previous clock cycle. Maxi-
mum access delay from the clock rise is 11.0 ns (66-MHz
device).
Write operations are controlled by the four Byte Write Select
(BWS[3:0]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
CLK
ADV/LD
A[16:0]
CEN
CE1
CE2
CE3
WE
BWS [3:0]
Mode
17
CONTROL
and WRITE
LOGIC
CE
DaDta-In
Q
REG.
36
36
128KX36
36
MEMORY
17 ARRAY
DQ[31:0]
DP[3:0]
OE
Selection Guide
.
7C1351-66
Maximum Access Time (ns)
11.0
Maximum Operating Current (mA)
Commercial
250 mA
Maximum CMOS Standby Current (mA)
Commercial
5 mA
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.
7C1351-50
12.0
200 mA
5 mA
7C1351-40
14.0
175 mA
5 mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 9, 1999

CY7C1351
Pin Configuration
DP2
DQ16
DQ17
VDDQ
VSS
DQ18
DQ19
DQ20
DQ21
VSS
VDDQ
DQ22
DQ23
VSS
VDD
VDD
VSS
DQ24
DQ25
VDDQ
VSS
DQ26
DQ27
DQ28
DQ29
VSS
VDDQ
DQ30
DQ31
DP3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100-Pin TQFP
CY7C1351
CY7C1351
80 DP1
79 DQ15
78 DQ14
77 VDDQ
76 VSS
75 DQ13
74 DQ12
73 DQ11
72 DQ10
71 VSS
70 VDDQ
69 DQ9
68 DQ8
67 VSS
66 VSS
65 VDD
64 VSS
63 DQ7
62 DQ6
61 VDDQ
60 VSS
59 DQ5
58 DQ4
57 DQ3
56 DQ2
55 VSS
54 VDDQ
53 DQ1
52 DQ0
51 DP0
2


Features www.DataSheet4U.com CY7C1351 128Kx36 F low-Through SRAM with NoBL™ Architect ure Features • Pin compatible and fun ctionally equivalent to ZBT™ devices IDT71V547, MT55L128L36F, and MCM63Z737 • Supports 66-MHz bus operations with zero wait states — Data is transferr ed on every clock • Internally self-t imed output buffer control to eliminate the need to use OE • Registered inpu ts for Flow-Through operation • Byte Write capability • 128K x 36 common I /O architecture • Single 3.3V power s upply • Fast clock-to-output times 11.0 ns (for 66-MHz device) — 12.0 ns (for 50-MHz device) • • • • • — 14.0 ns (for 40-MHz device) Clo ck Enable (CEN) pin to suspend operatio n Synchronous self-timed writes Asynchr onous Output Enable JEDEC-standard 100 TQFP package Burst Capability—linear or interleaved burst order Low standby power Functional Description The CY7C1 351 is a 3.3V, 128K by 36 Synchronous F low-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operatio.
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