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K4Y50084UC Dataheets PDF



Part Number K4Y50084UC
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description (K4Y50024UC - K4Y50164UC) 512Mbit XDR TM DRAM
Datasheet K4Y50084UC DatasheetK4Y50084UC Datasheet (PDF)

www.DataSheet4U.com K4Y50164UC K4Y50084UC K4Y50044UC K4Y50024UC XDRTM DRAM 512Mbit XDR TM DRAM(C-die) Revision 1.1 August 2006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS .

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www.DataSheet4U.com K4Y50164UC K4Y50084UC K4Y50044UC K4Y50024UC XDRTM DRAM 512Mbit XDR TM DRAM(C-die) Revision 1.1 August 2006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. XDR is a trademark of Rambus Inc. 1 of 76 Rev. 1.1 August 2006 K4Y50164UC K4Y50084UC K4Y50044UC K4Y50024UC XDRTM DRAM Change History Revision 1.0 1.1 Month December August Year 2005 2006 History - First Copy - Based on the Rambus XDRTM DRAM Datasheet Version 0.88 - Add comment on page 5 - Add TMIN on Table13, page 57 2 of 76 Rev. 1.1 August 2006 K4Y50164UC K4Y50084UC K4Y50044UC K4Y50024UC XDRTM DRAM 0.0 Overview The XDR DRAM device is a general-purpose high-performance memory device suitable for use in a broad range of applications, including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The 512Mb XDR DRAM device is a CMOS DRAM organized as 32M words by 16bits. The use of Differential Rambus Signaling Level(DRSL) technology permits 4000/3200/2400 Mb/s transfer rates while using conventional system and board design technologies. XDR DRAM devices are capable of sustained data transfers up to 8000 MB/s. XDR DRAM device architecture allows the highest sustained bandwidth for multiple, interleaved randomly addressed memory transactions. The highly-efficient protocol yields over 95% utilization while allowing fine access granuarity. The device’s eight banks support up to four interleaved transactions. 1.0 Features ♦ Highest pin bandwidth available - 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling ♦ Bi-directional differential RSL(DRSL) - Flexible read/write bandwidth allocation - Minimum pin count ♦ On-chip termination - Adaptive impedance matching - Reduced system cost and routing complexity ♦ Highest sustained bandwidth per DRAM device - Up to 8000 MB/s sustained data rate - Eight banks : bank-interleaved transaction at full bandwidth - Dynamic request scheduling - Early-read-after-write support for maximum efficiency - Zero overhead refresh ♦ Low Latency - 2.0/2.5/3.33ns request packets - Point-to-point data interconnect for fastest possible flight time - Support for low-latency, fast-cycle cores ♦ Low Power - 1.8V VDD - Programmable small-swing I/O signaling(DRSL) - Low power PLL/DLL design - Powerdown self-refresh support - Per pin I/O powerdown for narrow-width operation ♦ 0.49us refresh intervals(32K/16ms refresh) ♦ RoHS compliant 3 of 76 Rev. 1.1 August 2006 K4Y50164UC K4Y50084UC K4Y50044UC K4Y50024UC XDRTM DRAM 2.0 Key Timing Parameters/Part Numbers Organization Bandwidth (1/tBIT)a 2400 32Mx16 3200 4000 2400 64Mx8 3200 4000 2400 128Mx4 3200 4000 2400 256Mx2 3200 4000 Latency(tRAC)b 36 35 28 36 35 28 36 35 28 36 35 28 Binc A B C A B C A B C A B C Part Number K4Y50164UC-JCA2 K4Y50164UC-JCB3 K4Y50164UC-JCC4 K4Y50084UC-JCA2 K4Y50084UC-JCB3 K4Y50084UC-JCC4 K4Y50044UC-JCA2 K4Y50044UC-JCB3 K4Y50044UC-JCC4 K4Y50024UC-JCA2 K4Y50024UC-JCB3 K4Y50024UC-JCC4 a.Data rate measured in Mbit/s per DQ differential pair. See “Timing Conditions” on page 58 and “ Timing Characteristics” on page 60. Note that tBIT=tCYCLE/8 b.Read access time tRAC (= tRCD-R+tCAC) measured in ns. See “Timing Parameters” on page 61. c.Timing parameter bin. See “Timing Parameters” on page 61. This is a measure of the number of interleaved read transactions needed for maximum efficiency (the value Ceiling(tRC-R/tRR-D). For bin A, tRC-R/tRR-D=4, and for bin B, tRC-R/tRR-D=5 for bin C, tRC-R/tRR-D =6. 4 of 76 Rev. 1.1 August 2006 K4Y50164UC K4Y50084UC K4Y50044UC K4Y50024UC XDRTM DRAM 3.0 General Description The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins. The “N” appended to a signal name denotes the complementary signal of a differential pair. A transaction is a collection of packets needed to complete a memory access. A packet is a set of bit windows on the signals of a bus. There are two buses that carry packets: the RQ bus and .


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