A49LF040

A49LF040 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory Document Title 4 Mbit CMOS 3.3 Volt-only Low Pin Count Flash Memory Revision History Rev. No. 0.0 0.1 0.2 1.0 History Initial issue Add Pb-Free package type Change ordering information Hardware write protection disable Final version release Issue Date February 17, 2004 August 20, 2004 October 21, 2005 November 17, 2005 Remark Preliminary Final (November, 2005, Version 1.0) AMIC Technology, Corp. A49LF040 4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory FEATURES Single Power Supply Operation - Low voltage range: 3.0 V - 3.6 V for Read and Write Operations Standard Intel Low Pin Count Interface - Read compatible to Intel® Low Pin Count (LPC) interface Memory Configuration - 512K x 8 (4 Mbit) Block Architecture - 4Mbit: eight uniform 64KByte blocks - Supports full chip erase for Address/Address Multiplexed (A/A Mux) mode Automatic Erase and Program Operation - Embedded Byte Program and Block/Chip Erase algorithms - Typical 10 µs/byte programming time - Typical 1s block erase time Two Operational Modes - Low Pin Count Interface (LPC) Mode for in-system operation - Address/Address Multiplexed (A/A Mux) Interface Mode for programming equipment Low Pin Count (LPC) Mode - 33 MHz synchronous operation with PCI bus - 5-signal communication interface for in-system read and write operations - Standard SDP Command Set - Data# Polling (I/O7) and Toggle Bit (I/O6) features - 4 ID pins for multi-chip sel...