K7Q161862B

www.DataSheet4U.com K7Q163662B K7Q161862B Document Title 512Kx36-bit, 1Mx18-bit QDRTM SRAM 512Kx36 & 1Mx18 QDRTM b2 SRAM Revision History Rev. No. 0.0 1.0 History 1. Initial document. 1. Final spec release Draft Date Jan. 27, 2004 Mar. 18, 2004 Remark Advance Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Mar. 2004 Rev 1.0 K7Q163662B K7Q161862B 512Kx36-bit, 1Mx18-bit QDRTM SRAM FEATURES 1.8V/2.5V +0.1V/-0.1V Power Supply. I/O Supply Voltage 1.5V +0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O. Separate independent read and write data ports with concurrent read and write operation HSTL I/O. Full data coherency, providing most current data . Synchronous pipeline read with self timed early write. Registered address, control and data input/output. DDR(Double Data Rate) Interface on read and write ports. Fixed 2-bit burst for both read and write operation. Clock-stop supports to reduce current. Two input clocks(K and K) for accurate DDR timing at clock rising edges only. Two Input clocks for output data(C and C) to minimize clock-skew and flight-time mismatches. Single address bus. Byte writable function....