54LVTH162373 D-Type Latches Datasheet

54LVTH162373 Datasheet, PDF, Equivalent


Part Number

54LVTH162373

Description

3.3V 16-Bit Transparent D-Type Latches

Manufacture

Maxwell Technologies

Total Page 10 Pages
Datasheet
Download 54LVTH162373 Datasheet


54LVTH162373
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54LVTH162373
3.3V 16-Bit Transparent
D-Type Latches
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1 48
54LVTH162373
24 25
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
Logic Diagram (PositiveLogic)
1OE/2OE 1/24
1LE/2LE 48/25
1D1/2D1 47/36
C1
1D
To Seven Other Channels
Logic Diagram
2/13 1Q1/2Q1
FEATURES:
DESCRIPTION:
• 3.3V low voltage advanced BiCMOS technology (LVT) 16-
bit transparent D-type latches with 3-state outputs
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Excellent Single Event Effect:
- SELTH: No LU > 119 MeV/mg/cm2
• Package: 48 pin RAD-PAK® flat package
• Operating temperature range:
- 55 to 125°C
• Distributed VCC and GND pin configuration minimizes high-
speed switching noise
• Supports mixed-mode signal operation
- 5V input and output voltages with 3.3V VCC
• Supports unregulated battery operation down to 2.7V
• Supports live insertion
• Bus-hold data inputs eliminate the need for external pullup
resistors
Maxwell Technologies’ 54LVTH162373 16-bit transparent D-
type latches with 3-state output features a greater than 100
krad (Si) total dose tolerance, depending upon space mission.
The 54LVTH162373 is designed for low voltage (3.3V) VCC
operation, but with the capability to provide a TTL interface to
a 5V system environment. It is suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and working reg-
isters. The 54LVTH162373 can be used as two 8-bit latches or
one 16-bit latch. When the latch-enable (LE) input is low, the
Q output are latched at the levels set up at the data (D) inputs.
When LE is high, the Q outputs follow the D inputs. A buffered
output-enable (OE) input can be used to place the eight out-
puts in either a normal logic state or a high impedance state.
In the high impedance state, the outputs neither load nor drive
the bus lines significantly. The high impedance state and the
increased drive provide the capability to drive bus lines with-
out the need for interface or pullup components. OE does not
affect internal operations of the latch. Old data can be retained
or new data can be entered while the outputs are in the high
impedance state.
Maxwell Technologies' patented RAD-PAK® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, RAD-PAK provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
1000596
12.19.01 Rev 1
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
All data sheets are subject to change without notice 1
©2001 Maxwell Technologies
All rights reserved.

54LVTH162373
3.3V 16-Bit Transparent D-Type
54LVTH162373
TABLE 1. PINOUT DESCRIPTION
PIN
1, 24
2, 3, 5, 6, 8, 9, 11, 12
4, 10, 15, 21, 28, 34, 39, 45
7, 31, 42
13, 14, 16, 17, 19, 20, 22, 23
25, 48
26, 27, 29, 30, 32, 31, 32,
33, 35, 36
37, 38, 40, 41, 43, 44, 46, 47
SYMBOL
1OE-2OE
1Q1-1Q8
GND
VCC
2Q1-2Q8
2LE-1LE
2D8-2D1
1D8-1D1
DESCRIPTION
Output Enable
Outputs
Ground
Power Supply
Outputs
Latch Enable
Inputs
Inputs
TABLE 2. 54LVTH162373 ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNIT
Supply voltage range
VCC -0.5 4.6
Input voltage range 1
VI -0.5 7
Voltage range applied to any output in the high state or power-off
state 1
VO
-0.5
7
V
V
V
Current into any output in the low state
Current into any output in the high state 2
Input clamp current (VI < 0)
Output clamp current (VO < O)
Maximum power dissipation at TA = 55°C 3
Storage temperature range
IO -- 30 mA
IO -- 30 mA
IIK -- -50 mA
IOK -- -50 mA
PD -- 0.85 mW
TS -65 150 °C
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The maximum package power dissipation is calculated using a junction temperature of 150 °C and a board trace length of 750
mils.
TABLE 3. DELTA LIMITS
PARAMETER
ICC(OL)
ICC(OH)
ICC(OD)
VARIATION
±10% of specified value in Table 5
±10% of specified value in Table 5
±10% of specified value in Table 5
1000596
12.19.01 Rev 1
All data sheets are subject to change without notice 2
©2001 Maxwell Technologies
All rights reserved.


Features www.DataSheet4U.com PRELIMINARY 3.3V 1 6-Bit Transparent D-Type Latches 1OE 1Q 1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1 Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE 24 25 1 48 1LE 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 GND 1D7 1D8 54LVTH 162373 Logic Diagram (PositiveLogic) 1 /24 1OE/2OE 1LE/2LE 48/25 C1 1D1/2D 1 47/36 1D 2/13 1Q1/2Q1 54LVTH162373 2D1 2D2 GND 2D3 2D4 VCC 2D5 2D6 GND 2 D7 2D8 2LE To Seven Other Channels Lo gic Diagram Memory FEATURES: • 3.3V low voltage advanced BiCMOS technology (LVT) 16bit transparent D-type latches with 3-state outputs • Total dose ha rdness: - > 100 krad (Si), depending up on space mission • Excellent Single E vent Effect: - SELTH: No LU > 119 MeV/m g/cm2 • Package: 48 pin RAD-PAK® fla t package • Operating temperature ran ge: - 55 to 125°C • Distributed VCC and GND pin configuration minimizes hig hspeed switching noise • Supports mix ed-mode signal operation - 5V input and output voltages with 3.3V VCC • Supports unregulated battery operation down to.
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