ZL30123

www.DataSheet4U.com ZL30123 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet May 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30123GGG 100 Pin CABGA Trays ZL30123GGG2 100 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC DPLL2 provides a comprehensive set of features for generating derived output clocks and other general purpose clocks Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz Provides 3 sync inputs for output frame pulse alignment Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency Configurable input to output delay, and output to output phase alignment Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities Supports IEEE 1149.1 JTAG Boundary Scan Features Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 Internal APLL provides standard output clock frequencies up to 622.08 MHz with jitter < 3 ps RMS suitable for GR-253-CORE OC-12 and G.813 STM-16 interfaces Programmable output synthesizers (P0, P1) generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz Provides two DPLLs which are indep...