DatasheetsPDF.com

PI74SSTU32864 Dataheets PDF



Part Number PI74SSTU32864
Manufacturers Pericom Semiconductor
Logo Pericom Semiconductor
Description Configurable Registered Buffer
Datasheet PI74SSTU32864 DatasheetPI74SSTU32864 Datasheet (PDF)

www.DataSheet4U.com PI74SSTU32864 25-Bit 1:1 or 14-Bit 1:2 Configurable Registered Buffer Features • PI74 SSTU32864 is designed for low-voltage operation, VDD = 1.8V • Supports Low Power Standby Operation • All Inputs are SSTL_18 Compatible, except RST, C0, C1, which are LVCMOS. • Output drivers are optimized to drive DDR-II DIMM loads • Designed for DDR Memory • Packaging (Pb-free & Green available): -96 Ball LFBGA (NB) Description Pericom Semiconductor’s PI74SSTU32864 logic circuit is produc.

  PI74SSTU32864   PI74SSTU32864



Document
www.DataSheet4U.com PI74SSTU32864 25-Bit 1:1 or 14-Bit 1:2 Configurable Registered Buffer Features • PI74 SSTU32864 is designed for low-voltage operation, VDD = 1.8V • Supports Low Power Standby Operation • All Inputs are SSTL_18 Compatible, except RST, C0, C1, which are LVCMOS. • Output drivers are optimized to drive DDR-II DIMM loads • Designed for DDR Memory • Packaging (Pb-free & Green available): -96 Ball LFBGA (NB) Description Pericom Semiconductor’s PI74SSTU32864 logic circuit is produced using advanced CMOS technology. This 25-Bit 1:1 or 14-Bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V LVCMOS drivers that have been optimized to drive the DDR-II DIMM load. The SSTU32864 operates from a differential clock (CK and CK). Data is registered at the crossing of CK going high, and CK going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration for 25-Bit 1:1 (when LOW) to 14-Bit 1:2 (when HIGH). The device supports low-power standby operation. When the reset input (RST) is low, the differential input receivers are disabled and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition , when RST is low, all registers are reset, and all outputs are forced low. The LVCMOS RST and Cn inputs must always be held at a valid logic high or low level. 1D C1 R QCKEB* QODTA Block Diagram 1:2 Mode (Positive Logic) RST CK CK VREF DCKE QCKEA To ensure defined outputs from the register before a stable clock has been supplied, RST must be held in the low state during power up. In the DDR-II RDIMM application, RST is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST until the input receivers are fully enabled, the design of the SSTU32864 must ensure that the outputs remain low, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs will function normally. The RST input has priority over the DCS and CSR control will force the outputs low. If the DCS control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the set-up time requirement for DCS would be the same as for the other D data inputs. DODT 1D C1 R QODTB* DCS 1D C1 R QCSA QCSB* CSR D1 0 1 1D C1 R Q1A Q1B* TO OTHER CHANNELS Note: Disabled in 1:1 configuration 1 PS8636B 07/26/04 PI74SSTU32864 25-Bit 1:1 or 14-Bit 1:2 Configurable Buffer Pin Configuration 1:1 Register (C0 = 0, C1 = 0) 1 A B C D E F G H J K L M N P R T DCKE D2 D3 DODT D5 D6 NC CK CK D8 D9 D10 D11 D12 D13 D14 2 NC D15 D16 NC D17 D18 RST DCS CSR D19 D20 D21 D22 D23 D24 D25 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 5 QCKE Q2 Q3 QODT Q5 Q6 C1 QCS ZOH Q8 Q9 Q10 Q11 Q12 Q13 Q14 6 NC Q15 Q15 NC Q17 Q18 C0 NC ZOL Q19 Q20 Q21 Q22 Q23 Q24 Q25 Pin Configuration 1:2 Register (C0 = 0, C1 = 1) 1 A B C D E F G H J K L M N P R T DCKE D2 D3 DODT D5 D6 NC CK CK D8 D9 D10 D11 D12 D13 D14 2 NC NC NC NC NC NC RST DCS CSR NC NC NC NC NC NC NC 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 5 Q2A Q3A QODTA Q5A Q6A C1 QCSA ZOH Q8A Q9A Q10A Q11A Q12A Q13A Q14A 6 Q2B QODTB Q4B Q5B Q6B C0 QCSB ZOL Q8B Q9B Q10B Q11B Q12B Q13B Q14B QCKEA QCKEB 2 PS8636B 07/26/04 PI74SSTU32864 25-Bit 1:1 or 14-Bit 1:2 Configurable Buffer Pin Configuration 1:2 Register (C0 = 1, C1 = 1) 1 A B C D E F G H J K L M N P R T D1 D2 D3 D4 D5 D6 NC CK CK D8 D9 D10 DODT D12 D13 DCKE 2 NC NC NC NC NC NC RST DCS CSR NC NC NC NC NC NC NC 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 5 Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA ZOH Q8A Q9A Q10A Q12A Q13A 6 QB Q2B Q3B Q4B Q5B Q6B C0 QCSB ZOL Q8B Q9B Q10B Q12B Q13B QODTA QODTB QCKEA QCKEB NB 96-ball LFBGA (MO-205CC) Top View 3 PS8636B 07/26/04 PI74SSTU32864 25-Bit 1:1 or 14-Bit 1:2 Configurable Buffer Terminal Functions Name GND VDD VREF ZOH ZOL CK CK C0, C1 RST CSR, DCS D1, D25 DODT DCKE Q1-Q25 QCS QODT QCKE Gro.


NE687M33 PI74SSTU32864 PI74SSTV16857


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)