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PS21343-N Dataheets PDF



Part Number PS21343-N
Manufacturers Mitsubishi Electric Semiconductor
Logo Mitsubishi Electric Semiconductor
Description TRANSFER-MOLD TYPE INSULATED TYPE
Datasheet PS21343-N DatasheetPS21343-N Datasheet (PDF)

www.DataSheet4U.com MITSUBISHI MITSUBISHI SEMICONDUCTOR SEMICONDUCTOR Module> PS21343-N PS21343-N TRANSFER-MOLD TRANSFER-MOLD TYPE TYPE INSULATED INSULATED TYPE TYPE PS21343-N INTEGRATED POWER FUNCTIONS 600V/10A low-loss 4th generation (planar) IGBT inverter bridge for 3 phase DC-to-AC power conversion. INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS • For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting.

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www.DataSheet4U.com MITSUBISHI MITSUBISHI SEMICONDUCTOR SEMICONDUCTOR Module> PS21343-N PS21343-N TRANSFER-MOLD TRANSFER-MOLD TYPE TYPE INSULATED INSULATED TYPE TYPE PS21343-N INTEGRATED POWER FUNCTIONS 600V/10A low-loss 4th generation (planar) IGBT inverter bridge for 3 phase DC-to-AC power conversion. INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS • For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control circuit under-voltage (UV) protection. Note : Bootstrap supply scheme can be applied. • For lower-leg IGBTS : Drive circuit, Control circuit under-voltage protection (UV), Short-circuit protection (SC). • Fault signaling : Corresponding to a SC fault (Low-side IGBT) or a UV fault (Low-side IGBT). • Input interface : 5V line CMOS/TTL compatible, Schmitt Trigger receiver circuit. APPLICATION AC100V~200V inverter drive for motor control. Fig. 1 PACKAGE OUTLINES HEAT SINK SIDE (3.556) (1) TERMINAL (0.5) (3.556) (1.656) (0.5) Dimensions in mm TERMINAL CODE VUFS (UPG) VUFB VP1 (COM) UP VVFS (VPG) VVFB VP1 (COM) VP VWFS (WPG) VWFB VP1 (COM) WP (UNG) VNO(NC) UN VN WN FO CFO CIN VNC VN1 (WNG) (VNG) P U V W N (1) (0.5) DUMMY PIN (1.778 × 26) (1.778) (6.25) (6.25) (6.25) (8) (8) A (0.5) (30.5) (0.75) 29 30 Type name , Lot No. (φ3 .3) (17.4) (17.4) 28 27 26 25 24 23 22 21 20 19 18 16 17 15 13 14 12 10 11 987 654 321 D (φ2 EP TH 2) 35 34 33 32 31 (7.62 × 4) (41) (42) (49) (0.5) (7.62) (4MIN) 1 2 3 4 5 PCB 6 (1) PATTERN 7 8 (1.9) SLIT 9 (1.8MIN) 10 (PCB LAYOUT) 11 Detail A *Note2 12 13 (5) 14 15 16 17 18 19 20 21 22 23 HEAT SINK SIDE 24 (35 °) 25 26 27 28 29 30 31 32 33 (1.25) 34 (2.5) 35 (6.5) (10.5) (1.5) (1.2) *Note1:(***) = Dummy Pin. *Note 2: In order to increase the surface distance between terminals, cut a slit, etc. on the PCB surface when mounting a module. Sep. 2001 MITSUBISHI SEMICONDUCTOR PS21343-N TRANSFER-MOLD TYPE INSULATED TYPE Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE) CBW+ CBW– CBV+ CBV– CBU– CBU+ C3 : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance value depends on the PWM control scheme used in the applied system). C4 : 0.22~2µF R-category ceramic capacitor for noise filtering. High-side input (PWM) (5V line) (Note 1,2) Input signal Input signal Input signal coditioning coditioning coditioning Level shifter Level shifter Level shifter Protection circuit (UV) C4 C3 Protection circuit (UV) Protection circuit (UV) (Note 6) DIP-IPM Inrush current limiter circuit Drive circuit Drive circuit Drive circuit P H-side IGBTS AC input (Note 4) C Z U V W M AC line output Fig. 3 N1 VNC N CIN Drive circuit L-side IGBTS Z : ZNR (Surge absorber) C : AC filter (Ceramic capacitor 2.2~6.5nF) (Note : Additionally, an appropriate line to line surge absorber circuit may become necessary depending on the application environment.) Input signal conditioning Fo logic SC protection Control supply Under-Voltage protection FO CFO Low-side input (PWM) (5V line) (Note 1, 2) FO output (5V line) (Note 3, 5) Note1: 2: 3: 4: 5: 6: To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 6) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 6) This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kΩ resistance. (see also Fig. 6) The wiring between the power DC link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N1 DC power input terminals. tFO=1.8ms (Typ.)) Fo output pulse width should be decided by connecting external capacitor between CFO and VNC terminals. (Example : CFO=22nF High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. VNC VD (15V line) Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT DIP-IPM Drive circuit P Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault. IC (A) SC Protection Trip Level H-side IGBTS U V W L-side IGBTS External protection circuit N1 Shunt Resistor (Note 1) A N VNC CIN B Drive circuit.


PC113 PS21343-N PS9687L1


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