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TS83C51Rx2 Dataheets PDF



Part Number TS83C51Rx2
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description (TS8xC51Rx2) High Performance 8-bit Microcontrollers
Datasheet TS83C51Rx2 DatasheetTS83C51Rx2 Datasheet (PDF)

www.DataSheet4U.com TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 High Performance 8-bit Microcontrollers 1. Description Atmel Wireless & Microcontrollers TS80C51Rx2 is high performance CMOS ROM, OTP, EPROM and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C51Rx2 retains all features of the 80C51 with extended ROM/EPROM capacity (16/32/64 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt system, an on-chip oscilator and three timer/counte.

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www.DataSheet4U.com TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 High Performance 8-bit Microcontrollers 1. Description Atmel Wireless & Microcontrollers TS80C51Rx2 is high performance CMOS ROM, OTP, EPROM and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C51Rx2 retains all features of the 80C51 with extended ROM/EPROM capacity (16/32/64 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt system, an on-chip oscilator and three timer/counters. In addition, the TS80C51Rx2 has a Programmable Counter Array, an XRAM of 256 or 768 bytes, a Hardware Watchdog Timer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism. The fully static design of the TS80C51Rx2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C51Rx2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. 2. Features • 80C52 Compatible • 8051 pin and instruction compatible • Four 8-bit I/O ports • Three 16-bit timer/counters • 256 bytes scratchpad RAM High-Speed Architecture • 40 MHz @ 5V, 30MHz @ 3V • X2 Speed Improvement capability (6 clocks/ machine cycle) 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V) Dual Data Pointer bytes) • Hardware Watchdog Timer (One-time enabled with Reset-Out) • 2 extra 8-bit I/O ports available on RD2 with high pin count packages • • Asynchronous port reset • Interrupt Structure with • 7 Interrupt sources, • 4 level priority interrupt system Full duplex Enhanced UART • Framing error detection • Automatic address recognition Low EMI (inhibit ALE) • Idle mode • Power-down mode • Power-off Flag Once mode (On-chip Emulation) • • • On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K• On-chip eXpanded RAM (XRAM) (256 or 768 bytes) • Programmable Clock Out and Up/Down Timer/ Counter 2 • • Power Control modes • Programmable Counter Array with • • • • High Speed Output, Compare / Capture, Pulse Width Modulator, Watchdog Timer Capabilities • • Power supply: 4.5-5V, 2.7-5.5V • Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC) • Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44 (window), CDIL40 (window), PLCC68, VQFP64 1.4, JLCC68 (window) Rev. C - 06 March, 2001 1 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 PDIL40 PLCC44 VQFP44 1.4 TS80C51RA2 TS80C51RD2 TS83C51RB2 TS83C51RC2 TS83C51RD2 TS87C51RB2 TS87C51RC2 TS87C51RD2 0 0 16k 32k 64k 0 0 0 0 0 0 0 0 16k 32k 64k 256 768 256 256 768 256 256 768 512 1024 512 512 1024 512 512 1024 32 32 32 32 32 32 32 32 ROM (bytes) EPROM (bytes) XRAM (bytes) TOTAL RAM (bytes) I/O PLCC68 ROM (bytes) VQFP64 1.4 TS80C51RD2 TS83C51RD2 TS87C51RD2 0 64k 0 0 0 64k 768 768 768 EPROM (bytes) XRAM (bytes) TOTAL RAM (bytes) 1024 1024 1024 I/O 48 48 48 3. Block Diagram T2EX P5 RxD TxD Vcc Vss PCA ECI T2 (1) Watch Dog (3) (3) XTAL1 XTAL2 ALE/ PROG PSEN CPU EA/VPP RD WR (3) (3) Timer 0 Timer 1 INT Ctrl EUART RAM 256x8 (1) (1) (1) ROM /EPROM 0/16/32/64Kx8 XRAM 256/768x8 PCA Timer2 C51 CORE IB-bus Parallel I/O Ports & Ext. Bus Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 (2) (2) (3) (3) RESET T0 T1 (3) (3) P1 P2 P3 INT0 INT1 P0 P4 (1): Alternate function of Port 1 (2): Only available on high pin count packages (3): Alternate function of Port 3 2 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 4. SFR Mapping The Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories: • • • • • • • • • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P0, P1, P2, P3, P4, P5 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H Serial I/O port registers: SADDR, SADEN, SBUF, SCON Power and clock control registers: PCON HDW Watchdog Timer Reset: WDTRST, WDTPRG PCA registers: CL, CH, CCAPiL, CCAPiH, CCON, CMOD, CCAPMi Interrupt system registers: IE, IP, IPH Others: AUXR, CKCON Table 1. All SFRs with their address and their reset value Bit addressable 0/8 1/9 CH 0000 0000 B 0000 0000 P5 bit addressable 1111 1111 ACC 0000 0000 CCON 00X0 0000 PSW 0000 0000 T2CON 0000 0000 P4 bit addressable 1111 1111 IP X000 000 P3 1111 1111 IE 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8 TMOD 0000 0000 SP 0000 0111 1/9 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E TH0 0000 0000 TH1 0000 0000 AUXR XXXXXX00 CKCON XXXX XXX0 PCON 00X1 0000 7/F SBUF XXXX XXXX SADDR 0000 0000 AUXR1 XXXX0XX0 WDTRST XXXX XXXX WDTPRG XXXX X000 SADEN 0000 0000 IPH X000 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 P5 byte addressable 1111 1111 CMOD 00XX .


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