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PI90LVB16 Dataheets PDF



Part Number PI90LVB16
Manufacturers Pericom Semiconductor
Logo Pericom Semiconductor
Description 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver
Datasheet PI90LVB16 DatasheetPI90LVB16 Datasheet (PDF)

www.DataSheet4U.com 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI90LVB16 Features • • • • • • • • • • Master/Slave clock selection in a backplane application 160 MHz operation (typical) 100ps duty cycle distortion (typical) 50ps channel to channel skew (typi.

  PI90LVB16   PI90LVB16


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www.DataSheet4U.com 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 PI90LVB16 Features • • • • • • • • • • Master/Slave clock selection in a backplane application 160 MHz operation (typical) 100ps duty cycle distortion (typical) 50ps channel to channel skew (typical) 3.3V power supply design Glitch-free power on at CLKI/O pins Low Power design (16mA @ 3.3V static) Accepts small swing (300mV typical) differential signal levels Industrial temperature operating range (–40°C to +85°C) Available in 24-pin TSSOP Packaging (L) General Description 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver PI90LVB16 is a six-channel LVTTL clock distribution driver with 50 picosecond channel-to-channel skew. It translates one BLVDS (Bus Low-Voltage Differential Signaling) input signal into six LVTTLcompatible output signals for distribution to adjacent chips on the same board. The PI90LVB16 accepts BLVDS (300mV typical) differential input levels, and translates them to 3V CMOS output levels. The 160MHz PI90LVB16 can be the master clock, driving inputs of other clock I/O pins in a multipoint environment. It can also drive the BLVDS backplane with a separate channel acting as a return/ source LVTTL clock source. The master/slave clock selection of the driving source is controlled by the CrdCLKIN and the DE pins. An output enable pin OE, when high, forces all CLKOUT pins high. A backplane clock distribution network must be able to drive many transmission line stubs. The Bus LVDS feature of the PI90LVB16 is ideal for driving data transfers in large, high-performance backplane system applications. The device can be used as a source synchronous driver to distribute clock signals within data and telecommunications systems. Driver Mode Truth Table Input OE L L H H H DE L L L L H CrdCLKIN CLKI/O+ L H L H X L H L H Z Output CLKI/O– H L H L Z CLKOUT L H H H H Receive Mode Truth Table Input OE DE H L L H H H CrdCLKIN X X X (CLKI/O+)–(CLKI/O–) X VID ≥ 0.07V VID ≤ –0.07V Output CLKOUT H H L L = Low Logic State; H = High Logic State; X = Irrelevant Z = High Impedance Function Diagram CLKOUT0 CLKOUT1 OE CLKI/0+ R CLKI/0– Delay CLKOUT5 MUX D DE CrdCLKIN 1 PS8536A 05/21/01 PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Connection Diagram GND OE NC VCCA GNDA CLKI/0+ CLKI/0– GNDA CrdCLKIN NC DE GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 VCC CLKOUT0 GND CLKOUT1 VCC CLKOUT2 GND CLKOUT3 VCC CLKOUT4 GND CLKOUT5 24-Pin L 20 19 18 17 16 15 14 13 TSSOP Package Pin Description Pin Name CLKI/O+ CLKI/O– OE Pin # 6 7 2 Type I/O I/O I De s cription True (Positive) side of the differential clock input. Complementary (Negative) side of the differential clock input. OE; this pin is active Low. When High, this pin forces all CLKOUT pin High. When Low, CLK OUT pins logic state is determined by either the CrdCLKIN or VID at the CLKI/O pins with respect to the logic level at the DE pin. This pin has a weak pullup device to VCC. If OE is floating, then all CLK OUT pins will be High. DE; this pin is active Low. When Low, this pin enables the CardCLKIN signal to the CLKI/O pins and CLK OUT. When High the Driver is 3- State, the CLKI/O pins are inputs and determine the state of the CLK OUT pins. This pin has a weak pullup device to VCC. If DE is floating, then all CLKI/O pins are 3- State. Six Buffered clock (CMOS) outputs. Input clock from Card (CMOS level or TTL level). VCC; Analog VCCA (Internally separate from VCC, connect externally or use separate power supplies). No special power sequencing required. Either VCCA or VCC can be applied first, or simultaneously apply both power supplies. DE 11 I CLK OUT CrdCLK IN VCC 13,15,17,19,21,23 9 16,20,24 O I Power GND VCCA 1,12,14,18,22 4 Ground GND Power Analog VCCA (Internally separate from VCC, connect externally or use separate power supplies). No special power sequencing required. Either VCCA or VCC can be applied first, or simultaneously apply both power supplies. GNDA NC 5,8 3,10 Ground Analog Ground (Internally separate from Ground must be connected externally. No Connects. 2 PS8536A 05/21/01 PI90LVB16 3V Bus LVDS 1-to-6 Clock Buffer/Bus Transceiver 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Absolute Maximum Ratings(1) Supply Voltage .


MIC5321 PI90LVB16 PVDZ172NPBF


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