FIN3383

www.DataSheet4U.com FIN3385 FIN3383 FIN3384 FIN3386 Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers October 2003 Revised April 2005 FIN3385 FIN3383 FIN3384 FIN3386 Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers General Description The FIN3385 and FIN3383 transform 28 bit wide parallel LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low Voltage Differential Signaling) data streams. A phaselocked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock 28 bits of input LVTTL data are sampled and transmitted. The FIN3386 and FIN3384 receive and convert the 4/3 serial LVDS data streams back into 28/21 bits of LVTTL data. Refer to Table 1 for a matrix summary of the Serializers and Deserializers available. For the FIN3385, at a transmit clock frequency of 85MHz, 28 bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. These chipsets are an ideal solution to solve EMI and cable size problems associated with wide and high-speed TTL interfaces. Features s Low power consumption s 20 MHz to 85 MHz shift clock support s r1V common-mode range around 1.2V s Narrow bus reduces cable size and cost s High throughput (up to 2.38 Gbps throughput) s Internal PLL with no external component s Compatible with TIA/EIA-644 specification s Devices are offered 56-lead TSSOP packages Ordering Code: Order Number FIN3383MTD FIN3384MTD FIN3385MTD FIN3386MTD Packag...